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data sheet july 2001 l9310 line interface and line access circuit full-feature slic, ringing relay, and test access device introduction the agere systems inc. l9310 is a combination full- feature, ultralow-power slic, solid-state ringing access relay, and line test matrix. it is part of a pin- for-pin compatible family of devices designed to serve a wide variety of applications. the l9310 is optimized for european access applications and north american access where per-line testing and gr-909 longitudinal balance are required. features slic n 5 v and battery operation n optional automatic battery switch n 15 operational and test modes n appropriate for 46 db longitudinal balance applica- tions n minimal external components required at all inter- faces n ultralow power dissipation n software/hardware adjustable dc parameters and supervision thresholds n meter pulse compatible n ground start/ground key compatible solid-state ring relay n low impulse noise n current-limited switches/thermal protection line test matrix n single-ended or differential measurements n current or voltage sense n ac or dc measurements n dedicated analog input and output applications n pair gain n digital loop carrier (dlc) n central office (co) n fiber-in-the-loop (fitl) description the l9310 electronic line interface and line access circuit (lilac) provides all the functions that are nec- essary to interface a codec to the tip and ring of a subscriber loop, integrating the battery feed and ring- ing access relay and line test access in one low- power, low-cost package. the l9310 requires a 5 v and battery supply to oper- ate. included is an automatic battery switch. the bat- tery feed offers forward and reverse battery, on-hook transmission, ground start, ground key, and meter pulse operational modes. it also has a low-power scan and a disconnect mode. in all operating states, this ic is designed for minimal power dissipation. this device is designed to mini- mize the number of external components required at all interfaces. the dc template, current limit, and overhead voltage and loop supervision threshold are programmable via an applied voltage source. the voltage source may be an external programmable voltage source or derived from the v ref slic output. the integrated solid-state switch offers power ringing access. impulse noise is minimized, thus eliminating the need for external zero-cross switching circuitry. the l9310 provides line test capability. the differen- tial or single-ended ac and dc line voltage or current may be measured by the l9310.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 2 agere systems inc. table of contents contents page introduction..................................................................1 features....................................................................1 slic .......................................................................1 solid-state ring relay ...........................................1 line test marix.......................................................1 applications...............................................................1 description ................................................................1 features ......................................................................4 description...................................................................4 architecture .................................................................9 pin information ..........................................................10 operating states........................................................14 input state coding ..................................................14 state definitions ........................................................16 primary control modes ...........................................16 powerup, forward battery....................................16 powerup, reverse battery ...................................16 scan .....................................................................16 ground start.........................................................16 ringing .................................................................17 disconnect break before make .........................17 tip amp ................................................................17 ring amp .............................................................17 tip and ring amp.................................................17 reset....................................................................17 secondary control mode states .............................17 voltage: tip to ground .........................................17 voltage: ring to ground.......................................17 voltage: tip to ring..............................................17 current: tip to ringvtx ...................................18 current: tip to ringvitr ..................................18 reference voltage ...............................................18 ppm on................................................................18 ppm off/test off................................................18 special states .........................................................18 thermal shutdown ...............................................18 battery out of range ...........................................19 absolute maximum ratings ......................................19 electrical characteristics ...........................................20 ring trip detector...................................................21 ppm ........................................................................21 test ........................................................................22 slic two-wire port ................................................23 analog pin characteristics......................................25 ac feed characteristics ..........................................26 logic inputs and outputs, v dd = 5.0 v ...................27 timing requirements..............................................27 switch characteristics.............................................28 on-state switch i-v characteristics........................29 test configurations ...................................................30 applications ...............................................................32 dc characteristics ...................................................32 power control.......................................................32 power derating.....................................................32 automatic battery switch .....................................33 contents page power control resistor ....................................... 34 dc loop current limit .......................................... 34 overhead voltage ............................................... 35 loop range......................................................... 36 battery feed........................................................ 36 battery reversal rate ......................................... 37 longitudinal to metallic balance.......................... 37 supervision............................................................... 37 loop closure.......................................................... 37 ring trip ............................................................... 38 tip or ring ground detector.................................. 38 switching behavior................................................. 38 make-before-break operation ............................... 38 break-before-make operation ............................... 39 protection ................................................................. 39 external protection................................................. 39 active mode response at pt/pr........................... 40 ring mode response at pt/pr............................. 41 internal tertiary protection..................................... 41 diode bridge........................................................ 41 battery out of range detector: high (magnitude) ................................................. 41 battery out of range detector: low (magnitude) ................................................. 41 special functions ..................................................... 42 periodic pulse metering (ppm).............................. 42 line test ................................................................ 42 ac applications ......................................................... 44 ac parameters........................................................ 44 codec types .......................................................... 44 ac interface network .............................................. 44 design tools .......................................................... 45 first-generation codec ac interface network........ 45 first-generation codec ac interface network: resistive termination................... 46 example 1, real termination .............................. 47 hybrid balance....................................................... 47 first-generation codec ac interface network: complex termination ................... 50 complex termination impedance design .......... 50 ac interface using first-generation codec ......... 50 set z tg gain shaping ....................................... 50 transmit gain...................................................... 51 receive gain....................................................... 52 hybrid balance .................................................... 52 blocking capacitors............................................. 53 basic loop start application using t7504 type codec ................................................. 54 third-generation codec ac interface network: complex termination ................... 57 outline diagram........................................................ 59 44-pin plcc .......................................................... 59 ordering information................................................. 60
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 3 table of contents (continued) figures page figure 1. architecture diagram................................... 9 figure 2. test diagram............................................. 10 figure 3. 44-pin plcc ............................................. 10 figure 4. timing requirements ................................ 27 figure 5. on-state i-v characteristic ....................... 29 figure 6. basic test circuit ...................................... 30 figure 7. metallic psrr ........................................... 31 figure 8. longitudinal psrr .................................... 31 figure 9. longitudinal balance ................................. 31 figure 10. longitudinal impedance .......................... 31 figure 11. ac gains .................................................. 31 figure 12. l9310 loop/battery current (with battery switch) vs. loop resistance ....... 33 figure 13. tip/ring voltage ..................................... 36 figure 14. l9310 loop current vs. loop voltage..... 37 figure 15. ac equivalent circuit................................ 46 figure 16. agere t7504 first-generation codec resistive termination, nonmeter pulse application, single battery operation................................................. 48 figure 17. interface circuit using first-generation codec (blocking capacitors not shown) .................................................... 51 figure 18. ac interface using first-generation codec (including blocking capacitors) for complex termination impedance ...... 53 figure 19. basic loop start application using t7504 type codec .................................. 54 figure 20. l9310 for agere t8536 third-generation codec meter pulse application, dual battery operation, ac and dc parameters, fully programmable ................................ 57 tables page table 1. pin descriptions ..........................................11 table 2. primary control states ................................ 15 table 3. secondary control states ........................... 15 table 4. supervision coding..................................... 15 table 5. device operating conditions and powering ..................................................... 20 table 6. ring trip detector ....................................... 21 table 7. ppm ............................................................ 21 table 8. ac test source ............................................ 22 table 9. test sense .................................................. 22 table 10. slic two-wire port .................................. 23 table 11. analog pin characteristics ........................ 25 table 12. ac feed characteristics ............................ 26 table 13. logic inputs and outputs .......................... 27 table 14. timing requirements ................................ 27 table 15. break switches (sw1, 2) .......................... 28 table 16. ring return switch (sw3) ........................ 28 table 17. ringing access switch (sw4) .................. 29 table 18. typical active mode on- to off-hook tip/ring current-limit transient response .................................................. 35 table 19. fb1/fb2 values vs. typical ramp time .......................................................... 37 table 20. break-before-make logic control sequence device switching...................... 39 table 21. testlev output options......................... 43 table 22. l9310 parts list for agere t7504 first-generation codec resistive termina- tion, nonmeter pulse application, single battery operation ...................................... 49 table 23. l9310 parts list for agere t7504 first-generation codec complex termina- tion, meter pulse application, dual battery operation .................................................. 55 table 24. l9310 parts list for agere t8536 third-generation codec meter pulse applica- tion, dual battery operation, ac and dc pa- rameters, fully programmable.................. 58
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 4 agere systems inc. features n slic, solid-state ring relay, and line test access, inte- grated into a single package n 5 v and battery operation n user-defined power control options: automatic battery switch power control resistor package thermal capabilities n minimal external components required n operating states: forward active reverse active (controlled rate of reversal) scan ground start (tip open) all-off or disconnect ring periodic pulse metering (ppm) active modes line test modes (dc/ac line voltage/current) n ultralow power: scan, 15 mw active states, on-hook, 75 mw ring mode, on-hook, 90 mw disconnect, 10 mw n adjustable overhead voltage: default overhead adequate for 3.14 db into 900 w overload controlled rate of overhead adjustment n latched parallel input data interface with reset n interrupt (unlatched) based loop status monitor n adjustable current limiter: 10 ma to 70 ma programming range n adjustable loop closure detector with hysteresis: 4 ma detect, 2.5 ma no detect minimum, upper limit of 15 ma detect hysteresis, typical 20% of programmed on-hook to off-hook threshold n ring trip detector: single-pole filtering n thermal shutdown protection with hysteresis n line break switch will foldover into a low-current state under high-voltage fault conditions n battery out-of-range monitor circuit: all-off upon loss of battery (low battery condition) all-off upon high battery (fault condition) n longitudinal balance: etsi/itu-t, gr-909 balance n ground start: tip open state ring ground detector n ground key: tip/ring ground detector n meter pulse compatible: dedicated meter pulse signal input on-hook transmission of ppm (up to 5 vrms) provides convenient access for hybrid filtering of meter pulse n line test: line test modes (ac or dc): 1. voltage tip to ground 2. voltage ring to ground 3. voltage tip to ring 4. current tip to ring 5. current tip to ground 6. current ring to ground inject test tones through codec interface or dedi- cated input pin analog output at dedicated output pin n rfi/emc-en 300 386-2 v1.1.3 (1997-12) n integrated 2 form c ring relay: low impulse noise current-limited switches break-before-make and make-before-break switching n meets itu-t k20, itu-t k21, and telcordia * gr1089 requirements with external protection device n 44-pin, surface-mount plastic package (plcc) description the l9310 electronic line interface and line access cir- cuit (lilac) provides all the functions that are neces- sary to interface a codec to the tip and ring of a subscriber loop, integrating the battery feed and ringing access relay in one low-power, low-cost package. the physical construction of the device is two chips. the first chip is manufactured in agere 90 v complemen- tary bipolar integrated circuit (cbic-s) technology. this chip contains the slic functionality: n ac transmission path n dc feedback and functions n active dc current limit n active mode loop supervision n thermal shutdown * telcordia is a trademark of bell communications research, inc.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 5 description (continued) the second chip is manufactured in agere dielectrically isolated 320 v bipolar cmos diffused metal oxide semiconductor (bcdmos iii) technology. this chip contains the following: n ring access relay n scan clamp circuitry n logic control n ring trip n te s t n ppm n thermal shutdown n battery monitor circuit the lilac family requires a +5 v and battery supply to operate. no C5 v supply is required. a battery switch is included that automatically, based on subscriber loop length, will apply either the primary higher-voltage bat- tery or an optional lower-voltage auxiliary battery. use of this feature will minimize off-hook power dissipation. the switch point is a function of the user-programmed dc current limit and the magnitude of the auxiliary bat- tery. switching from the high-voltage to low-voltage battery is quiet, without interruption of the dc loop cur- rent, thus preventing any impulse noise generation at the switch point. design equations for the switch point and a graph showing loop/battery current versus loop resistance are given in the dc characteristics section of this data sheet. if the user does not want to provide an auxiliary battery, the design of the l9310 battery switch allows use of a power control resistor at the auxiliary battery input. this scheme will not reduce short-loop, off-hook power dis- sipation, but it will control power dissipation on the slic by sharing power among the slic, power resis- tor, and dc loop. however, in most cases, without the auxiliary battery, the power dissipation capabilities of the 44-pin plcc package are adequate so that the power control resistor will not be needed. design equa- tions for power control options are given in the dc char- acteristics section of this data sheet. the l9310 has two active transmission ready states, forward active and reverse active. both on-hook and off-hook transmission are provided during the forward and reverse battery modes. battery reversal is quiet, without breaking the ac path. rate of battery reversal may be ramped to control switching time via optional external capacitors . equations relating rate of battery reversal to these optional external capacitors are given in the dc characteristics, power control section of this data sheet. a low-power scan mode is available to reduce idle mode on-hook power. this mode is realized by using a scan clamp circuit. in low-power scan mode: n the scan clamp circuitry is active. n loop closure is active. n all ac transmission, dc feed, and other supervision circuits, including ring trip, are shut down. n ppm and test are powered down. n thermal shutdown is active. n low battery sense shutdown is on. n on-hook transmission is disabled. when the scan clamp circuitry is on, overhead voltage is fixed and not controlled by ovh. when the scan clamp is on, current limit is not controlled by v prog ; rather, it is set by the internal capabilities of the scan clamp circuit. see the dc loop current limit and over- head voltage sections of this data sheet for more details. a forward disconnect mode, where all circuits are turned off and power is denied to the loop, is also pro- vided. during this mode, the nstat supervision output will read on hook. in the ring mode, the line break switches are opened and the power ring access switches are closed. in this mode, the ring trip detector in the slic is active and all other detectors and the tip/ring drive amplifiers are turned off to conserve power. make-before-break or break-before-make switching is achievable during ring cadence or ring trip. toggling directly into or directly out of the ring mode table will give make-before-break switching. to achieve break- before-make switching, go to an intermediate all-off state (use forward disconnect state), before entering the ring mode or before leaving the ring mode. see the switching behavior section of this data sheet for more details on switching behavior. voltage transients or impulse noise associated with ring cadence or ring trip are minimized or eliminated with the l9310, thus possibly eliminating the need for external zero-cross switching circuitry. a tip open switch configuration is also available for ground start applications. a common-mode current detector is included for ground start and ground key applications.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 6 agere systems inc. description (continued) both the ring trip and loop closure supervision func- tions are included. loop closure threshold is set by applying a voltage source to the lcth input. the volt- age source may be an external voltage source or derived from the slic v ref output. a programmable external voltage source may be used to provide soft- ware control of the loop closure threshold. design equations for the loop closure threshold are given in the supervision section of this data sheet. hysteresis is included. the ring trip detector requires only a single-pole filter at the input. this will minimize the required number of external components. to help minimize device power dissipation, the ring trip detector is active only during the power ring mode. ring trip and loop supervision status outputs appear in a common output pin, nstat. nstat is an unlatched supervision output; thus, an interrupt-based control scheme may be used. the dc current limit is set in the active modes via an applied voltage source. the voltage source may be an external voltage source. the voltage may be derived via a resistor divider network from the v ref slic out- put. a programmable external voltage source may be used to provide software control of the loop closure threshold. design equations for this feature are given in the dc characteristics section of this data sheet. programming range is 10 ma to 70 ma, with a maxi- mum 2.5 vrms meter pulse at tip and ring. program- ming range is 10 ma to 45 ma, with a maximum 5 vrms meter pulse at tip and ring. overhead is programmable in the active modes via an applied voltage source. the voltage source may be an external voltage source or derived via a resistor divider network from the v ref slic output. a programmable external voltage source may be used to provide software control of the overhead voltage. a potential application of this feature is to increase over- head during meter pulse injection and reduce overhead during periods of nonmeter pulse injection. the rate of change of the overhead voltage may be controlled by use of a single external capacitor at the c f1 node. if the rate of change is uncontrolled, there may be audible noise associated with this transition. design equations for this feature are given in the dc characteristics sec- tion of this data sheet. if the overhead is not programmed via a resistor, the device develops a default overhead adequate for a 3.14 dbm overload into 900 w . for the default over- head, ovh is connected to ground. overhead is not changed when the ppm input is turned on. sufficient overhead to pass meter pulse signals must be set at ovh input. the l9310 provides line test capability. in the test mode, a voltage proportional to the ac or dc tip to ground, ring to ground, tip to ring voltage or current may be presented at the slic testlev output. an ac test tone may also be applied to a test input, testsig, or through the codec rcvn/rcvp interface. testsig input is active upon entering a test state and remains active after leaving the test mode. by varying the frequency of the applied test tone, parameters such as line capacitance may be measured. testsig should be externally connected to the devices v ref if it is not used during a test condition. this may be done by a high-impedance pull-up resis- tor. additionally, testsig should be ac coupled to the test signal generator. test level outputs at testlev are referenced to the internally generated reference voltage v ref . this refer- ence voltage may also be output at testlev so the users can compensate test results at testlev for the internal reference. note that during nontest modes, testlev is high impedance to conserve power. input testsig is turned off during any nontest mode and during the v ref test mode.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 7 description (continued) the various test modes are achieved through a series of integrated analog switches that can reconfigure the slic to provide normal slic operation or the appropri- ate test function. details are given in the special func- tions, line test section of this data sheet. test modes are achieved through the device state table. when entering a test mode, the state of the slic is unchanged; thus, testing can be done with the slic in forward and reverse battery active modes. addition- ally, via the line break switches associated with the ring relay, use of a tip open or ring open state is used to make single-ended voltage and current measurements. data control is via a parallel latched data control scheme. data latches are edge-level sensitive. data is latched in when the latch control input goes low. while latch is low, the user cannot change the data control inputs. the data control inputs may only be changed when latch is high. incorporation of data latches allows for data control information and loop supervision information to be passed to and from the slic via data buses rather than on a per-line basis, thus minimizing routing complexity and board routing area. a device reset pin is included. when this pin is low, the logic inputs are overridden and the device will be reset into slic forward disconnect state and the switch into the all-off state. nstat is forced to the on-hook condition when r eset is low. the overall device protection is achieved through a combination of an external secondary protector, along with an integrated thermal shutdown feature, a battery voltage window comparator, the break switch foldback characteristic, and the dc/dynamic current-limit response of the break and tip return switches. for protection against long duration fault conditions, such as power cross and tip/ring shorts, a thermal shut- down mechanism is integrated into the device. upon reaching the thermal shutdown temperature, the device will enter an all-off mode. upon cooling, the device will re-enter the state it was in prior to thermal shutdown. hysteresis is built in to prevent oscillation. during this mode, the nstat supervision output overrides the actual loop status and forces an off-hook. the line break switches and tip return switch are current-limited switches. the current-limit mechanism limits current through the switch to the specified dc cur- rent limit under low frequency or dc faults (power cross and/or tip/ring to ground short) and limits the current to the specified dynamic current-limit response under transient faults, such as lightning. a foldover characteristic is incorporated into the line break switches within their i-v curve. under voltage conditions higher than the normal operating range, such as may be seen under an extreme lightning or power cross fault condition, the line break switch will foldover into a low-current state. this feature allows for more relaxed specifications on the ring side protector, thus allowing for higher-voltage ringing signals. (tip side protector is limited by the requirements on the tip return switch.) this feature is part of the overall device protection scheme. this device uses a window comparator to force an all- off condition if the battery drops below, or rises above, a specified threshold. upon loss of v bat1 , the l9310 will automatically enter an all-off mode. the device will enter this mode if the magnitude of the battery drops below a nominal 15 v and will remain in this mode until the magnitude of the battery rises above a typical 20 v. during this mode, the nstat supervision output will override the actual hook status and force an off-hook or logic low. when the device is in the scan mode, because of the design of the scan clamp circuit, common-mode cur- rent can be forced into or out of the battery supply. because of this, and depending upon power supply design, the magnitude of the battery may rise above the maximum operating condition during extended lon- gitudinal currents or during a power cross fault condi- tion. to prevent excess current from being forced into or out of the battery, if the magnitude of the battery rises typically above 75 v to 80 v, the device will enter an all-off state. the device will remain in the all-off state until the magnitude of the battery drops into the normal operating range. during this mode, the nstat supervi- sion output will override the actual hook status and force an off-hook or logic low. see the protection section of this data sheet for more details on device protection. please contact your agere account representative for a recommended secondary protection device. longitudinal balance is consistent with european etsi and north american gr-909 requirements.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 8 agere systems inc. description (continued) the l9310 will support the ppm application. a low-volt- age ppm is injected at the ppmin pin. ppmin is a high-impedance input that controls the ppm differential voltage on tip and ring. the ppm signal may be present at this pin at all times; however, ppm will only be transmitted to tip and ring during a ppm active mode . activating or deactivating the ppmin input will not change the state of the slic device. the slic may change states while the ppmin input is active. design equations relating the magnitude of the ppm signal output at tip and ring to the ppm input signal at ppmin and information on ppm cancellation are given in the special functions, periodic pulse metering sec- tion of this data sheet. no ppm shaping is done by the l9310 device. it is assumed that a shaped ppm input is presented to ppmin. maximum allowed ppm and dc current limit are related by the overall drive capabilities of the tip and ring drive amplifiers. these amplifiers can support up to 70 ma dc current limit with a maximum 2.5 vrms meter pulse signal at tip and ring. these amplifiers can support up to 45 ma dc current limit with a maximum 5 vrms meter pulse signal at tip and ring. if on-hook transmission of ppm is required, sufficient overhead to accommodate on-hook transmission must be programmed by the user at the ovh input. over- head is not increased during a ppm active mode. overhead may be changed during ppm active and ppm not active modes by a change to the voltage pro- grammed at the ovh input. see the overhead voltage section of the dc characteristics section for more detail. filtering of the meter pulse signal in the transmit direc- tion may be necessary to prevent overload at the codec inputs. note that ppmout is provided as a con- venient point to perform rejection of the meter pulse. via a resistor from ppmout to node itr, a portion of the ppm signal that is injected to tip and ring is phase inverted and fed back to the transmit path to provide a hybrid cancellation of the meter pulse signal in the transmit direction. this method of hybrid cancellation is adequate for 2.5 vrms meter pulse. however, for higher-voltage meter pulse, such as 5 vrms, additional filtering may be necessary. this may be done by a filter network at the txn input. transmit and receive gains have been chosen to mini- mize the number of external components required in the slic-codec ac interface, regardless of the choice of codec. the l9310 uses a voltage feed, current sense architec- ture; thus, the transmit gain is a transconductance. the l9310 transconductance is set via a single external resistor, and this device is designed for optimal perfor- mance with a transconductance set at 300 v/a. the l9310 offers an option for a single-ended to differ- ential receive gain of either 8 or 2. these options are mask programmable at the factory and are selected by choice of part number. a receive gain of 8 is more appropriate when choosing a first-generation type codec where termination imped- ance, hybrid balance, and overall gains are set by external analog filters. the higher gain is typically required for synthesization of complex termination impedance. a receive gain of 2 is more appropriate when choosing a third-generation type codec. third-generation codecs will synthesize termination impedance, set hybrid bal- ance, and set overall gains. to accomplish these func- tions, third-generation codecs typically have both analog and digital gain filters. for optimal signal-to- noise performance, it is best to operate the codec at a higher gain level. if the slic then provides a high gain, the slic output may be saturated, causing clipping dis- tortion of the signal at tip and ring. to avoid this situa- tion with a higher-gain slic, external resistor dividers are used. these external components are not neces- sary with the lower gain offered by the l9310. the rcvp/rcvn slic inputs are floating inputs. if there is not feedback from rcvp/rcvn to vitr, rcvp/rcvn may be directly coupled to the codec out- put. if there is feedback, rcvp/rcvn must be ac-cou- pled to the codec output. this device is packaged in a 44-pin plcc surface- mount package.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 9 architecture 12-3523 (f) figure 1. architecture diagram C + aac + C ax 2.35 v bandgap reference test rft tip/ring current sense bgnd itr/325 v ref vitr rfr v bat bgnd v bat itr itr ring trip detector scan & ring gnd detector scan clamp scan v bat bgnd rt ilc ac interface x1 x1 switchhook window comparator in ref cf2 current limiter and inrush control cf2 ref parallel data interface v ref txn txi itr trng pt testlev pr rts rsw rring vtx v cc a gnd trgdet icm v bat2 /pwr v bat v bat1 v bat1 bgnd bgnd ppmout ppmin rcvp rcvn fb1 cf1 ovh cf2 fb2 testsig fbrb dc ac dgnd v dd v prog b0 b1 b2 b3 latch reset lcth lcf vitr control rt ilc fb rb vtx in +5v d (1 v/50 ma) sw3 sw1 18 w 60 w sw2 18 w +5v a v bat v bat bgnd bgnd + C out at + C out ar fb nstat 2.35 v v ref vtx sw4 15 w
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 10 agere systems inc. architecture (continued) 12-3525c (f) figure 2. test diagram pin information 12-3522 (f) figure 3. 44-pin plcc v ref pt pr v dd v dd dgnd dgnd testlev 66.7 k w + C test block vitr vtx 5 m w 5 m w 66.7 k w 7 9 10 11 12 13 14 15 16 17 8 6 4 3 2 1 4443424140 5 18 20 21 22 23 24 25 26 27 28 19 39 37 36 35 34 33 32 31 30 29 38 l9310ap 10 fb2 lcf rpwr v bat1 v bat1 bgnd testsig ppmin testlev fb1 bgnd cf1 v prog ovh v ref lcth v cc agnd rcvn rcvp vitr cf2 txi itr icm trgdet dgnd v dd latch reset b0 txn vtx ppmout rsw rring pr pt tring nstat b3 b2 b1 rts
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 11 pin information (continued) table 1. pin descriptions pin symbol type name/function 1 lcth i loop closure program input. connect a voltage source or ground, via a resistor, to this point to program the loop closure threshold. 2v ref o slic internal reference voltage. output of internal 2.35 v slic reference volt- age. 3ovh i overhead voltage program input. connect a voltage source to this point to pro- gram the overhead voltage. voltage source may be external or derived via a resistor divider from v ref . a programmable external voltage source may be used to provide software control of the overhead voltage. if a resistor or voltage source is not con- nected, the overhead voltage will default to approximately 5.5 v (sufficient to pass 3.14 dbm in to 900 w ). if the default overhead is desired, connect this pin to ground. 4v prog i current-limit program input. connect a voltage source to this point to program the dc current limit. voltage source may be external or derived via a resistor divider from v ref . a programmable external voltage source may be used to provide soft- ware control of the loop closure threshold. 5cf2 filter capacitor. connect a 0.1 m f capacitor from this node to ground for filtering. 6cf1 filter capacitor. connect a capacitor from this node to ovh to control the rate of change of the overhead voltage. if controlled overhead is not desired, leave this node open. 7fb2 polarity reversal slowdown capacitor. connect a capacitor from this node to ground to control the rate of battery reversal. if controlled battery reversal is not desired, leave pin is open. 8fb1 polarity reversal slowdown capacitor. connect a capacitor from this node to ground to control the rate of battery reversal. if controlled battery reversal is not desired, leave pin is open. 9lcf loop closure filter capacitor. ppm injection can cause false loop closure indica- tion. connect a capacitor from this node to v cc to filter the loop closure detector. if loop closure filtering is not required, leave this node open. 10 bgnd g battery ground. ground return for the battery supply. 11 rpwr p auxiliary battery. if a lower-voltage auxiliary battery is used, connect the auxiliary battery supply to this node. if a power control resistor is used, connect the power control resistor from this node to v bat1 . if no power control technique is used, con- nect this node to v bat1 . 12 v bat1 p office battery supply. negative high-voltage power supply. 13 v bat1 p office battery supply. negative high-voltage power supply. 14 bgnd g battery ground. ground return for the battery supply. 15 testsig i test input. this input injects a test signal to the line when an appropriate test oper- ational state is chosen. connect this node to v ref if not used. 16 ppmin i receive ppm signal input. this high-impedance input controls the ppm differen- tial voltage on tip and ring. the ppm signal may be present at this pin at all times; however, ppm will only be transmitted to tip and ring if the appropriate active-ppm state is chosen. ac couple ppm signal to this node. connect this node to v ref if not used.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 12 agere systems inc. pin information (continued) table 1. pin descriptions (continued) pin symbol type name/function 17 testlev o test level output. this output pin will provide a voltage that is proportional to either the dc line voltage, dc line current, ac line voltage, ac line current, or internal refer- ence voltage, dependent upon which operational state is selected. 18 ppmout o ppm out. connect a resistor from this node to itr for hybrid cancellation of meter pulse signal. 19 rts i ring trip sense. sense input for the ring trip detector. 20 rsw o ring lead ringing access switch. ringing relay connects this pin to pin rring. connect this pin to pin pr through a 400 w current-limiting resistor. 21 rring i ringing access. input to solid-state ringing access switch. connect to ringing gen- erator. 22 pr i/o protected ring. the output of the ring driver amplifier and input to loop sensing connected through solid-state break switch. connect to subscriber loop through overvoltage/current protection. 23 pt i/o protected tip. the output of the tip driver amplifier and input to loop sensing con- nected through solid-state break switch. connect to subscriber loop through over- voltage/current protection. 24 tring o tip ringing return. ring relay connects this pin to pt. connect to ringing supply return. 25 nstat o loop status. the output of the loop status detector (loop start detector wired-or with ring trip detector). this loop status supervision output is not controlled by the data latch. 26 b3 i data control input. see table 2, primary control states and table 3, secondary control states for details. 27 b2 i data control input. see table 2, primary control states and table 3, secondary control states for details. 28 b1 i data control input. see table 2, primary control states and table 3, secondary control states for details. 29 b0 i data control input. see table 2, primary control states and table 3, secondary control states for details. 30 reset i reset. a logic low will override the b[0:3] and latch inputs and reset the state of the slic to the disconnect state and the switch to the all-off state. 31 latch i latch control input. edge-level sensitive control for data latches. 32 v dd p 5 v digital power supply. 5 v supply for digital circuitry. 33 dgnd g digital ground. ground return for v dd current. 34 trgdet o tip/ring ground detect. when high, this open collector output indicates the pres- ence of a ring ground or a tip ground. this supervision output may be used in ground start, ground key, or common-mode fault detection applications. it has an internal pull-up. 35 icm i common-mode current sense. to program tip or ring ground sense threshold, connect a resistor to ground and connect a capacitor to agnd to filter 50 hz/60 hz. if unused, the pin is connected to ground. 36 vtx o tip/ring voltage output. this output is a voltage that is directly proportional to the differential tip/ring current. a resistor from this node to itr sets the device transim- pedance. gain shaping for termination impedance with a combo i codec is also achieved with a network from this node to itr.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 13 pin information (continued) table 1. pin descriptions (continued) pin symbol type name/function 37 itr i transmit gain. a current output which is proportional to the differential current flowing from tip to ring. input to ax amplifier. connect a resistor from this node to vtx to set transmit gain to 300 w . hybrid reject of meter pulse is done by a resis- tor from this node to ppmout. gain shaping for termination impedance with a combo i codec is also achieved with a network from this node to vtx. 38 txn i transmit ac input (inverting). for higher-voltage meter pulse signals (5 vrms), connect a network to this node for meter pulse filtering. if lower-voltage meter pulse is used and meter pulse rejection is done via ppmout, this node is not used. this node has an internal connection to v ref ; thus, it may be left floating if unused. 39 txi i transmit ac input (noninverting). connect a 0.1 m f capacitor from this pin to vtx for dc blocking. 40 vitr o transmit ac output voltage. the output is a voltage that is directly proportional to the differential ac tip/ring current. this output is connected via a proper inter- face network to the codec. 41 rcvp i receive ac signal input (noninverting). this high-impedance input controls the ac differential voltage on tip and ring. 42 rcvn i receive ac signal input (inverting). this high-impedance input controls the ac differential voltage on tip and ring. 43 agnd g analog ground. ground return for v cc current. 44 v cc p 5 v analog power supply. 5 v supply for analog circuitry.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 14 agere systems inc. operating states input state coding state control is via a tiered logic system. the device must initially be set to a primary control state (b3 = 0). this will set the operational state of the slic and switch. the secondary control table (b3 = 1) is used to turn on the ppm amplifier or to turn on the test circuitry and enter a test state. the primary state of the device (the state of the slic and switch) will not change when entering a secondary control state. within the primary control table, each state will set the slic and the switch to a specific mode. the exception is the tip-amp and ring-amp states. the tip-amp and ring-amp states will change the configuration of the switches, but leave the state of the slic unchanged from the previous primary control mode. once a primary (device) control state is selected, the ppm or test circuitry can be activated via a secondary control state. within the secondary control table, there are ppm active modes and test active modes. upon entering a test active mode in the secondary control table, both testlev output and testsig input are active and the test switches set to the appropriate con- dition. (see test architecture diagram, figure 2.) an exception is the v ref test active mode. upon entering v ref , only the testlev output is active, and the inter- nal (2.35 v typical) reference voltage appears at testlev. in the v ref mode, the testsig input is deactivated. once ppm is on, the user may reverse the battery in the primary state table without turning off ppm. with ppm, if the user goes to the scan, ring, or disconnect mode in the primary table, ppm will be turned off. unlike ppm, the test feature, once on, will remain on if the user transitions to forward active, reverse active, scan, ring, or disconnect state in the primary state table. ppm or test is deactivated by selecting ppm/test off in the secondary control table. data control is via a parallel latched data control scheme. data latches are edge-level sensitive. data is latched in when the latch control input goes low. data must be set up 200 ns before latch goes low and held 50 ns after latch goes high. while latch is low, the user should not change the data control inputs at b0, b1, b2, and b3. the data control inputs at b0, b1, b2, and b3 may only be changed when latch is high. nstat supervision output is not controlled by the latch control input.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 15 operating states (continued) input state coding (continued) table 2. primary control states table 3. secondary control states table 4. supervision coding b3 b2 b1 b0 reset state 00001scan 00011powerup, forward battery 00101powerup, reverse battery 00111tip and ring amp 01001ring 01011tip amp 01101ring amp 01111disc onnect, break before make xxxx0disc onnect, break before make b3 b2 b1 b0 type active state 1000testtestlev, testsigtip/ring voltage 1001testtestlev, testsigtip voltage 1010testtestlev, testsigring voltage 1011testtestlev, testsigvtx current 1100testtestlev v ref 1101testtestlev, testsigvitrcurrent 1110ppmppmin, ppmoutppm on 1111ppmppm off ppm off/test off pin nstat pin trgdet 0 = off-hook or ring trip 0 = ring ground 1 = on-hook and no ring trip 1 = no ring ground
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 16 agere systems inc. state definitions primary control modes powerup, forward battery n normal talk and battery feed state. n pin pt is positive with respect to pin pr. n all ac transmission and dc feed circuits are powered up. n on-hook transmission is enabled. n thermal shutdown is active. n battery window comparator sense shutdown is on. n switch break switches (sw1 and sw2) are closed, and ring access switches (sw3 and sw4) are open. n v bat1 is applied to tip and ring during on-hook condi- tions. n automatic battery switch selects v bat1 or v bat2 dur- ing off-hook conditions. n all supervision circuits except for ring trip detector are active. n overhead is set via pin ovh. n testlev output is in the high-impedance mode, and testsig input is off unless this feature is selected via the secondary control table. n ppmout is in the high-impedance mode, and ppmin input is off unless this feature is selected via the secondary control table. n nstat represents the loop closure detector status. powerup, reverse battery n normal talk and battery feed state. n pin pr is positive with respect to pin pt. n all ac transmission and dc feed circuits are powered up. n on-hook transmission is enabled. n thermal shutdown is active. n battery window comparator sense shutdown is on. n switch break switches (sw1 and sw2) are closed, and ring access switches (sw3 and sw4) are open. n v bat1 is applied to tip and ring during on-hook condi- tions. n automatic battery switch selects v bat1 or v bat2 under off-hook conditions. n all supervision circuits except for ring trip detector are active. n overhead is set via pin ovh. n testlev output is in the high-impedance mode, and testsig input is off unless this feature is selected via the secondary control table. n ppmout is in the high-impedance mode, and ppmin input is off unless this feature is selected via the secondary control table. n nstat represents the loop closure detector status. scan n scan clamp circuitry is active. n loop closure is active. n all ac transmission, dc feed, and other supervision circuits, including ring trip, are shut down. n ppm is powered down. n thermal shutdown is active. n battery window comparator sense shutdown is on. n on-hook transmission is disabled. n pin pt is positive with respect to pr, and v bat1 is applied to tip/ring. n switch break switches (sw1 and sw2) are closed, and ring access switches (sw3 and sw4) are open. n when the scan clamp circuitry is on, overhead volt- age is fixed and not controlled by ovh. also the cur- rent limit is not the normal current limit set at v prog . n nstat represents the loop closure detector status. ground start n tip amplifier is on, tip break switch is open. n the device presents a high impedance (>100 k w ) to pin pt and a current-limited battery (v bat2 ) to pr. n common-mode current detector is on. n ring trip detector is off. n output trgdet indicates current flowing in the ring lead. n this is not a defined state in the primary control mode table. it is achieved via the powerup and the ring amp states in the primary control mode table.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 17 state definitions (continued) primary control modes (continued) ringing n switch break switches (sw1 and sw2) are open, and ring access switches (sw3 and sw4) are closed. n tip/ring drive amplifiers are powered down. n ring trip circuit is active. n loop supervision and common-mode current detec- tors are powered down. n nstat represents the ring trip detector status. disconnect break before make n the tip and ring amplifiers are turned off to conserve power. n break switches (sw1 and sw2) are open, and ring access switches (sw3 and sw4) are open. this mode is also used as a transitional mode to achieve break-before-make switching from the power ring to active or scan mode. n all supervision circuits are powered down; nstat overrides the actual loop condition and is forced high (on-hook). tip amp n tip side break switch is closed, and ring side break switch and ring access switches are open. n slic mode is unaffected by reconfiguring the ring relay via this mode; thus, slic will remain in the mode it was in prior to selecting this mode. ring amp n ring side break switch is closed; tip side break switch and ring access switches are open. n slic mode is unaffected by reconfiguring the ring relay via this mode; thus, slic will remain in the mode it was in prior to selecting this mode. tip and ring amp n tip and ring side break switches are open; ring access switches are open. n slic mode is unaffected by reconfiguring the break switches via this mode; thus, slic will remain in the mode it was in prior to selecting this mode. n this is the calibration mode for differential and sin- gle-ended tip/ring current measurements. reset n selection of device reset via the reset pin will set the device into the disconnect break-before-make state. secondary control mode states voltage: tip to ground n a voltage proportional to the tip to ground voltage appears at the testlev output. n testsig input is on. n customer applies ac test tone or v ref to testsig to select an ac or dc measurement. voltage: ring to ground n a voltage proportional to the ring to ground voltage appears at the testlev output. n testsig input is on. n customer applies ac test tone or v ref to testsig to select an ac or dc measurement. voltage: tip to ring n a voltage proportional to the differential tip to ring voltage appears at the testlev output. n testsig input is on. n customer applies ac test tone or v ref to testsig to select an ac or dc measurement.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 18 agere systems inc. state definitions (continued) secondary control mode states (continued) current: tip to ring vtx n a voltage proportional to the ac, plus dc tip to ring dif- ferential current, tip to ground current, or ring to ground current appears at the testlev output. use this state for dc measurements. n choice is determined by primary control mode table. n differential current is selected by choosing powerup forward or reverse from the primary control mode table. n tip to ground or ring to ground current is selected by first choosing powerup forward or reverse from the primary mode table, and then choosing tip amp or ring amp from the primary mode table. n testsig input is on. n customer applies ac test tone or v ref to select an ac or dc measurement. current: tip to ringvitr n a voltage proportional to the ac tip to ring differential current, tip to ground current, or ring to ground cur- rents, appears at testlev output. use this state for ac measurements. n choice is determined by primary control mode table. n differential current is selected by choosing powerup forward or reverse from the primary control mode table. n tip to ground or ring to ground current is selected by first choosing powerup forward or reverse from the primary mode table, and then choosing tip amp or ring amp from the primary mode table. n testsig input is on. n customer applies ac test tone or v ref to select an ac or dc measurement. reference voltage n a voltage proportional to the internal dc reference voltage v ref appears at the testlev output. n testsig input is off. n this is the calibration state for voltage measure- ments. ppm on n the ppmin input is activated and the ppm signal at ppmin is transmitted to tip and ring. n device mode per primary control mode table. once ppm is active, transition to the scan, disconnect, or ring modes in the primary state table will deactivate ppmin. transition to forward battery, reverse battery, ring amp, or tip amp state will not deactivate ppmin. ppm off/test off n the ppmin input is deactivated and the ppm signal at ppmin does not appear at tip and ring. n ppmout is high impedance. n device mode is per primary control mode table. n the testsig input is deactivated. n testlev output is high impedance. n device mode is per primary control mode table. special states thermal shutdown n not controlled via truth table inputs. n this mode is caused by excessive heating of the device, such as may be encountered in an extended power cross situation. n upon reaching the thermal shutdown temperature, the device will enter an all-off mode. n upon cooling, the device will re-enter the state it was in prior to thermal shutdown. n hysteresis is built in to prevent oscillation. in this mode, supervision output nstat is forced low (off-hook) regardless of loop status or if the discon- nect logic state is selected.
da t a s h eet j u ly 2 001 f u ll- f eat u r e s l ic, ri n gi n g re l a y , a n d t e s t ac c ess de v ice l 931 0 li n e in t e r fac e an d l i ne ac c ess ci r c u it agere sys t e m s i nc. 19 s t ate definition s (contin u ed) s pe ci al s t at e s ( c o n t i nued) battery o u t o f r a n g e n n o t con t ro l led via t ruth t able inp u t s . n t his mo d e i s cause d by a batter y out o f range; that i s , t he batter y vol t a g e risi n g a bov e o r be l o w a specified threshol d . n u p o n re a c h ing t he specified h i g h o r low batter y vol t ag e , t h e d e v i c e wi l l en t e r an al l - o f f mo d e . n u p on t he ba t t e r y ret u r n ing to t he s p e c i f i ed n ormal o p erat i ng ra n ge, t he de v i c e w il l re-en t er t he s tate it w a s in p r i o r to t he low batter y shu t dow n . n hysteresis i s bui l t in t o prevent os c i llation. i n this m ode, s u pervision output ns t a t is f orced low (o f f - h ook) re g ardless of loop s t a t u s or i f th e d isconnect l o gic s t ate is sel e c ted. absolute m aximum rating s ( a t t a = 25 c) s t resses in excess o f the a b s o lute max i mum ratings can cause per m ane n t da m age t o the device. th e s e are abso- lute stres s r a t i n g s onl y . fu n c tio n al op e r a t i o n of t h e devic e is not i m pl i ed at these or a n y o t h e r conditions i n excess of those given in t h e o p era t i onal sec t i o ns of the da t a sheet . e xposur e to absolute m a x i m u m ra t i ngs for ex t en d ed peri o d s ca n adversely a f f e ct d e v i c e rel i abil i t y . n o t e : t h e i c c a n b e da m a g e d u n l e s s a ll g r o u n d c o n n e c t i o n s a r e a p p l i e d b e f o r e , a n d r e mo v e d a f t e r , a l l o t h e r c o n n ec t i o n s . f u r t h e r m o r e , w h en p o w e r i n g t h e d e v i c e, t h e u s e r m u st g u a r a n tee t h at no e x t e r n al p ot e n t i a l c r e at e s a v o lta g e on a ny p i n of t h e d e v i c e t h at e x c e e ds t h e d ev i c e r a t i n g s . f o r e x am p l e , i n d u c t a n c e i n a s u p p l y l ea d c o u l d r e s on a t e w i t h t h e s u p p l y f i l t e r c a p a c i t o r t o c a u s e a d es t r u c t i v e o v e r v o l t - a ge. p ara m e t e r s y m bol m in m ax u n it 5 v dc s upp l ies ( v c c + v dd ) C0 . 5 7 . 0 v high o f fice bat t e r y supply (v b a t 1 ) C75 0 . 5 v a u x i liary o f f i c e bat t ery s u pply ( v b a t 2 ) v b a t 1 t o 0. 5 v v ringi n g v ol t a g e 1 1 0 v r m s logic i n p u t v o l t age C0 . 5 v cc + 0 . 5 v v max i mum j u nc t i o n t e m perature 165 c s torage t e m peratur e r a nge C40 125 c re l at i ve hu m i d i t y ra n ge 5 9 5 % s w i t ch 1, 2, 3 ; p ole t o p ole 320 v s w i t ch 4; p ole to p o l e 465 v s w i t ch i n pu t to o u t p ut 320 v
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 20 agere systems inc. electrical characteristics in general, minimum and maximum values are testing requirements. however, some parameters may not be tested in production because they are guaranteed by design and device characterization. typical values reflect the design center or nominal value of the parameter; they are for information only and are not a requirement. minimum and maximum values apply across the entire temperature range ( C40 c to +85 c) and entire battery range (C36 v to C70 v). unless otherwise specified, typical is defined as 25 c, v cc = v dd = 5.0, v bat1 = C48 v v bat2 = C25 v. positive currents flow into the device. table 5. device operating conditions and powering * not to exceed 26 grams of water per kilogram of dry air. parameter min typ max unit temperature range C40 85 c humidity range 5 95* %rh v bat1 operational range C36 C48 C72 v v bat2 operational range C19 C25 v bat1 v 5 v dc supplies (v cc , v dd )4.755.05.25v supply currents, scan state no loop current, v bat = C48 v, v cc = v dd = 5 v: i vcc+vdd i vbat1 power dissipation 2 100 15 2.5 200 22 ma m a mw supply currents, forward/reverse active no loop current, with on-hook transmission, ppm not active, test not active, v bat = C48 v, v cc = v dd = 5 v: i vcc+vdd i vbat1 power dissipation 6 1.1 83 6.5 1.4 100 ma ma mw supply currents, forward disconnect, v bat = C48 v, v cc = v dd = 5 v: i vcc+vdd i vbat1 power dissipation 1.2 65 9 1.85 275 22.5 ma m a mw supply currents, ring state, no loop current, v bat = C48 v, v cc = v dd = 5 v, v ring = 80 vrms: i vcc+vdd i vbat1 i ring generator power dissipation 4 200 500 70 ma m a m a mw power adders, v cc = v dd = 5 v, power for ppm and test amplifiers drawn only from 5 v supply: ppm te s t 1 5 mw mw psrr 500 hz3000 hz: v bat1 , v bat2 v cc 45 30 db db thermal protection shutdown (t tsd ) 150 165 c
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 21 electrical characteristics (continued) ring trip detector table 6. ring trip detector 1. the ringing source may be either of the following: a.) the ringing source consists of the ac and dc voltages added together (battery-backed ringing); the ringing return is ground. b.) the ringing source consists of only the ac voltage (earth-backed ringing); the ringing return is the dc voltage. 2. ndet must also indicate ring trip when the ac ringing voltage is absent (<5 vrms) from the ringing source. 3. pretrip ringing must not be tripped by a 10 k w resistor in parallel with an 8 f capacitor applied across tip and ring. ppm table 7. ppm 1. ppm signal should be ac coupled into ppmin. 2. this parameter is not tested in production, it is guaranteed by design and characterization. parameter min typ max unit voltage at input that will cause ring trip after appropriate zero crossings 2.5 3 3.5 v voltage at input that will cause immediate ring trip 12 15 18 v ringing source 1 : frequency (f) dc voltage ac voltage 19 C39.5 60 20 28 C57 105 hz v vrms ring trip (ndet = 0) 2, 3 : loop resistance trip time ndet valid 2000 200 80 w ms ms parameter min typ max unit ppm source 1 : frequency (f1) frequency (f2) input signal 11.88 15.80 12 16 12.12 16.20 1.0 khz khz vrms signal gain (from ppmin to amplifier outputs) 9 10 11 harmonic distortion 2 5 % isolation (nontest states) 65 db isolation (test modes) 50 db
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 22 agere systems inc. electrical characteristics (continued) test table 8. ac test source 1. ac test signal should be ac coupled into testsig. 2. a pull-down resistor to v ref should be connected to testsig. 3. this parameter is not tested in production, it is guaranteed by design and characterization. table 9. test sense 1. this is the voltage coefficient with respect to tip/ring voltage. see table 21 testlev output options (tip-to-ring, tip-to-gr ound, and ring- to-ground equations) for application of this parameter. 2. this parameter is not tested in production, it is guaranteed by design and characterization. parameter min typ max unit test source 1, 2 : frequency (f1) signal gain (testsig to amplifier outputs) v testsig = 0.35 v signal gain voltage coefficient input signal harmonic distortion 3 0 10 1.27 100 1.25 5 khz 1/v vrms % parameter min typ max unit single-ended voltage gain 10 v on tip/ring 1/75 differential voltage gain 10 v on tip/ring 1/75 voltage gain accuracy (single-ended or differential) C3.5 3.5 % voltage coefficient 0.01 1 %/v current gain at vtx (dc) differential 19.6 20 20.4 v/a current gain at vtx (dc) single-ended 9.8 10 10.2 v/a current gain at vitr (ac) differential 291 300 309 v/a current gain at vitr (ac) single-ended 145.5 150 154.5 v/a overload at vtx 2 105 ma overload at vitr 2 7 ma v ref 2.35v v ref accuracy C5 5 % testlev offset relative to v ref C40 40 mv testlev amplifier output voltage swing input voltage swing agnd + 0.35 agnd + 0.35 v cc C 0.4 v cc C 1.0 v v
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 23 electrical characteristics (continued) slic two-wire port table 10. slic two-wire port parameter min typ max unit pt and pr drive current = dc + longitudinal + signal currents + ppm 105 mapeak signal current 10 marms longitudinal current capability per wire (longitudinal current is indepen- dent of dc loop current) 8.5 15 marms ppm signal current (2.5 vrms max into 200 w ac) 12.5 marms ppm signal current (5 vrms max into 200 w ac) 25 marms dc active mode loop current C i lim (r loop = 100 w ): programming range (2.5 vrms max into 200 w ac) voltage at v prog 10 0.2 70 1.4 ma v dc active mode loop current C i lim (r loop = 100 w ): programming range (5 vrms max into 200 w ac) voltage at v prog 10 0.2 0 45 0.9 ma v dc current-limit variation: v prog = 0.8 v (i limit = 40 ma) 5 % loop resistance range (from pt/pr) (3.17 dbm overload into 600 w ): i loop = 20 ma at v bat1 = C48 v 1900 w v ref 2.23 2.35 2.47 v offset at v prog C40 40 mv dc feed resistance (includes internal slic dc resistance and break switch resistance) 50 75 110 w dv/dt sensitivity at pt/pr 200 v/ m s ground start state pt resistance 100 k w powerup open loop voltages (v bat1 = C48 v): forward/reverse active mode | pt C pr | C v bat1 (programming range) voltage at ovh (programming voltage) forward/reverse active mode | pt C pr | C v bat1 (ovh to gnd) common mode 5.5 0 5.5 6.1 (v bat1 + 1)/2 15 1.9 v v v v
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 24 agere systems inc. electrical characteristics (continued) slic two-wire port (continued) table 10. slic two-wire port (continued) * guarantees 46 db from 300 hz to 3.4 khz, with 50 w , 1% protection, resistors into a complex resistive termination impedance. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc. parameter min typ max unit powerup open loop voltages: scan mode | pt C pr | C v bat1 0 13.5 v loop closure threshold: voltage at lcth 0 v ref v loop closure threshold hysteresis 20 % ground key/ground start: gain icm to trgdet common-mode detector threshold 5 1 10 m a/ma ma longitudinal to metallic balance at pt/pr* (test method: q552 [11/96] section 2.1.2, ieee ? std. 455): 300 hz to 600 hz 600 hz to 3.4 khz 54 54 db db metallic to longitudinal (harm) balance: 200 hz to 4000 hz 40 db
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 25 electrical characteristics (continued) analog pin characteristics table 11. analog pin characteristics * this parameter is not tested in production. it is guaranteed by design and device characterization. parameter min typ max unit txn and txi (input impedance) 75 105 k w v prog input bias current* (current flow out of pin) C50 C250 na v oh input bias current* (current flow out of pin) C50 C250 na lcth input bias current* (+ current flows into pin) 50 250 na vtx: output offset output drive current output voltage swing (1 ma load): maximum minimum output short-circuit current output load resistance* output load capacitance* 1 agnd agnd + 0.35 10 50 40 v cc v cc C 0.4 50 mv ma v v ma k w pf vitr: output offset output drive current output voltage swing (1 ma load): maximum minimum output short-circuit current output load resistance* output load capacitance* 1 agnd agnd + 0.35 10 50 100 v cc v cc C 0.4 50 mv ma v v ma k w pf rcvn and rcvp: input voltage range (v cc = 5.0 v) input bias current 0 v cc C 0.5 1.5 v m a
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 26 agere systems inc. electrical characteristics (continued) ac feed characteristics table 12. ac feed characteristics 1. set externally either by discrete external components or a third- or fourth-generation codec. any complex impedance r1 + r2 | | c between 150 w and 1400 w can be synthesized. 2. this parameter is not tested in production. it is guaranteed by design and device characterization. 3. vitr transconductance depends on the resistor from itr to vtx. this gain assumes an ideal 6.34 k w , the recommended value. positive cur- rent is defined as the differential current flowing from pt to pr. parameter min typ max unit ac termination impedance 1 150 600 1400 w total harmonic distortion (200 hz 4 khz) 2 : off-hook on-hook 0.3 1.0 % % transmit gain 3 f = 1004 hz, 1020 hz: pt/pr current to vitr C291 C300 C309 v/a receive gain, f = 1004 hz, 1020 hz open loop: rcvp or rcvn to ptpr (gain = 8) rcvp or rcvn to ptpr (gain = 2) 7.76 1.94 8 2 8.24 2.06 ac feed resistance (includes internal slic ac resistance and break switch resistance) 50 75 110 w gain vs. frequency (transmit and receive) 2 900 w = 2.16 m f termi- nation, 1004 hz reference: 200 hz300 hz 300 hz3.4 khz 3.4 khz20 khz 20 khz266 khz C0.3 C0.05 C3.0 0 0 0 0.05 0.05 0.05 2.0 db db db db gain vs. level (transmit and receive) 2 0 dbv reference: C55 db to +3.0 db C0.05 0 0.05 db idle-channel noise (tip/ring) 600 w termination: psophometric c-message 3 khz flat C82 8 C77 13 20 dbmp dbrnc dbrn idle-channel noise (vtx) 600 w termination: psophometric c-message 3 khz flat C82 8 C77 13 20 dbmp dbrnc dbrn
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 27 electrical characteristics (continued) logic inputs and outputs, v dd = 5.0 v table 13. logic inputs and outputs timing requirements table 14. timing requirements data control is via a parallel latched data control scheme. data latches are edge-level sensitive. data is latched in when the latch control input goes low. data must be set up t su ns before latch goes low and held t hl ns after latch goes high. while latch is low, the user should not change the data control inputs at b0, b1, b2, and b3. the data control inputs at b0, b1, b2, and b3 may only be changed when latch is high. nstat supervision out- put is not controlled by the latch control input. 12-3526(f) figure 4. timing requirements parameter symbol min typ max unit input voltages: low level high level v il v ih C0.5 2.0 0.4 2.4 0.7 v dd v v input current: low level (v dd = 5.25 v, v i = 0.4 v) high level (v dd = 5.25 v, v i = 2.4 v) i il i ih 50 50 m a m a output voltages (cmos): low level (v dd = 4.75 v, i ol = 180 m a) high level (v dd = 4.75 v, i oh = C20 m a) v ol v oh 0 2.4 0.2 0.4 v cc v v parameter symbol min typ max unit minimum setup time from b0, b1, b2, b3 to latch t su 200 ns minimum hold time from latch to b0, b1, b2, b3 t hl 50 ns t su t hl latch b0, b1, b2, b3
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 28 agere systems inc. electrical characteristics (continued) switch characteristics table 15 . break switches (sw1, 2) 1. at 25 c, maximum voltage rating has a temperature coefficient of 0.167 v/ c. 2. this parameter is not tested in production. it is guaranteed by design and device characterization. 3. applied voltage is 100 vp-p square wave at 100 hz to measure dv/dt sensitivity. table 16. ring return switch (sw3) 1. at 25 c, maximum voltage rating has a temperature coefficient of 0.167 v/ c. 2 . this parameter is not tested in production. it is guaranteed by design and device characterization. 3 . applied voltage is 100 vp-p square wave at 100 hz to measure dv/dt sensitivity. parameter min typ max unit off state: maximum differential voltage dc leakage current (vsw = 320 v) 320 1 20 v a on state (see on-state i-v switch characteristics section): resistance maximum differential voltage (v max ) 2 foldback voltage breakpoint 1 (v1) foldback voltage breakpoint 2 (v2) dc current limit 1 (i limit 1) dc current limit 2 (i limit 2) dynamic current limit 10 x 700 m s, 1000 v applied surge t < 0.5 m s 72 v1 + 0.5 105 2 18 250 2.5 28 320 450 w v v v ma ma a dv/dt sensitivity 2, 3 200 v/s parameter min typ max unit off state: maximum differential voltage dc leakage current (vsw = 320 v) 320 1 20 v a on state (see on-state switch i-v characteristics section): resistance maximum differential voltage (v max ) 2 dc current limit dynamic current limit 10 x 700 m s, 1000 v applied surge t = 0.5 m s 60 200 2.5 100 130 w v ma a dv/dt sensitivity 2, 3 200 v/s
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 29 electrical characteristics (continued) switch characteristics (continued) table 17. ringing access switch (sw4) 1. choice of secondary protector and feed resistor should ensure these ratings are not exceeded. a minimum 400 w feed resistor is recom- mended. 2. this parameter is not tested in production. it is guaranteed by design and device characterization. 3. applied voltage is 100 vp-p square wave at 100 hz to measure dv/dt sensitivity. on-state switch i-v characteristics parameter min typ max unit off state: maximum differential voltage dc leakage current (vsw = 475 v) (pole to pole) isolation 475 20 320 v a v on state (see on-state switch i-v characteristics section): resistance voltage steady-state current 1 surge current (10 x 700 m s pulse) 2 release current 500 15 3 150 2 w v ma a m a dv/dt sensitivity 2, 3 200v/s 5-5990.c(f) a. line break switch sw1, sw2 12-3291.a(f) b. ring return sw3 12-3292.a(f) c. ring access sw4 figure 5. on-state switch i-v characteristics i lim1 i sw +1.5 2/3 r on r on C1.5 Ci lim1 +v max v sw i lim2 Ci lim2 +v 2 +v 1 Cv max Cv 2 Cv 1 Cv max Ci limit +i limit +v max v sw +1.5 v C1.5 v r on 2/3 r on current limiting i sw 2/3 r on current limiting Cv os +v os v sw r on i sw r on
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 30 agere systems inc. test configurations 12-3524h(f) figure 6. basic test circuit tring rring rsw rts pr pt ovh v prog lcth v ref lcf fb1 fb2 cf1 cf2 testsig testlev ppmin ppmout txi vtx itr txn pwr/ v bat1 v dd d gnd icm trgdet nstat tring ring tip v ref v cc fb1 fb2 cf1 50 w 50 w r loop 0.1 m f 0.1 m f 0.1 m f 0.1 m f v bat2 /pwr v bat1 v cc v dd gnd trgdet nstat b0 b0 b1 b1 b2 b2 b3 b3 latch latch reset reset 0.1 m f l9310 basic test circuit txn ppmout ppmin ring v bat2 bgnd v cc a gnd 6.34 k w rsw rts ovh v prog lcth 100 w/ 600 w 235 k w 1000 pf 0.01 m f testsig testlev 0.1 m f 0.1 m f rcvp rcvn vitr vitr rcv 4.13 k w v ref 20 k w 20 k w (gain = 2) 46.4 k w (gain = 8)
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 31 test configurations (continued) psrr = 20 log 12-2582 (f) figure 7. metallic psrr psrr = 20 log 12-2583 (f) figure 8. longitudinal psrr * ansi is a registered trademark of the american national stan- dards institue, inc. ansi */ ieee standard 455-1985 12-2584 (f) figure 9. longitudinal balance 12-2585 (f) figure 10. longitudinal impedance 12-2587.g (f) figure 11. ac gains v s 4.7 f 100 w v bat or v cc disconnect v t/r 900 w v bat or v cc pt pr basic test circuit + C capacitor bypass v s v t/r --------- - v s 4.7 f 100 w v bat or v cc disconnect bypass 56.3 w v bat or v cc pt pr basic test circuit 67.5 w 10 f 10 f 67.5 w v m + C capacitor v s v m ------ - pt pr basic test circuit longitudinal balance = 20 log v s v m 368 w 100 m f 100 m f 368 w v m + C v s pt pr basic test circuit + C + C i long i long v pt v pr z long = or d v pt d i long d v pr d i long pt pr basic test circuit 600 w v t/r + C g xmt = vitr v t/r g rcv = v t/r v rcv rcv v s vitr rcv vitr
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 32 agere systems inc. applications dc characteristics power control under normal device operating conditions, thermal design must ensure that the device temperature does not rise above the thermal shutdown. power dissipation is highest with higher battery voltages, with higher cur- rent limit, and under shorter dc loop conditions. higher ambient temperature will reduce thermal margin. power control may be done in several ways, by use of the integrated automatic battery switch and a lower- voltage auxiliary battery or by use of a power control resistor with single battery operation. the thermal capability of the 44-pin plcc package is sufficient to allow for single battery operation without the power control resistor when the device is used under lower- power operating conditions. power derating operating temperature range, maximum current limit, maximum battery voltage, minimum dc loop length, and protection resistors values, number of pcb board lay- ers, and airflow, will influence the overall thermal per- formance. the still-air thermal resistance of the 44-pin plcc package is typically 38 c/w for a two-layer board with 0 lfpm airflow. the l9310 will enter thermal shutdown at a tempera- ture of 150 c. the thermal design should ensure that the slic does not reach this temperature under normal operating conditions. for this example, assume a maximum ambient operat- ing temperature of 85 c, a maximum current limit of 30 ma, and a maximum battery of C56 v. further assume a (worst-case) minimum dc loop of 20 w for wire resistance, 50 w protection resistors, and 200 w for the handset. include the effects of parameter toler- ance in these calculations. t tsd C t ambient(max) = allowed thermal rise 150 c C 85 c = 65 c allowed thermal rise = package thermal impedance x slic power dissipation 65 c = 38 c/w x slic power dissipation allowed slic power dissipation (p d ) = 1.71 w thus, in this example, if the total power dissipated on the slic is less than 1.71 w, it will not enter thermal shutdown. total slic power is calculated: to ta l p d = maximum battery x (maximum current limit) (current limit accuracy) + slic quiescent power. for the l9310, the worst-case slic on-hook active qui- escent power is 100 mw. thus, total off-hook power = (i loop )(1.05) x (v batapplied ) + slic quiescent power total off-hook power = (0.030 a)(1.05) x (52) + 100 mw total off-hook power = 1.864 w the power dissipated in the slic is the total power dis- sipation less the power that is dissipated in the loop. slic p d = total power C loop power loop off-hook power = (i loop x 1.05) 2 x (r loopdcmin + 2r p + r handset ) loop off-hook power = {(0.030 a)(1.05)} 2 x (20 w + 100 w + 200 w ) loop off-hook power = 317.5 mw slic off-hook power = total off-hook power C loop off- hook power slic off-hook power = 1.864 w C 0.3175 w slic off-hook power = 1.5465 w < 1.71 w thus, under the operating conditions of this example, the thermal capability of the 44-pin plcc package is adequate to ensure that the l9310 will not be driven into thermal shutdown and no additional power control measures are needed. if, however, for a given set of operating conditions, the thermal capabilities of the package are not adequate to ensure the slic is driven into thermal shutdown, then one of the power control techniques described below should be used. addition- ally, even if the thermal capability of the 44-pin plcc package is adequate to ensure that the l9310 will not be driven into thermal shutdown, the battery switch technique described below can be used to reduce total short-loop power dissipation.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 33 applications (continued) dc characteristics (continued) automatic battery switch use of the automatic battery switch controls power dis- sipation by automatically switching to the lower-voltage auxiliary battery under short dc loop conditions, thus reducing the short-loop power that is generated. this has the advantage of not only controlling device tem- perature rise, but reducing overall power dissipation. the switch will automatically apply the appropriate bat- tery to support the dc loop. no logic control is needed to control the switch. switching is quiet, and the dc loop current will not be interrupted when switching between batteries. the lower-voltage auxiliary battery is con- nected to the v bat2 /prw package pin. the equation governing the switch point is as follows: r loop = C 2r p C r dc a graph showing loop and battery current versus loop resistance with use of the battery switch is shown in figure 12. the v bat2 voltage must be chosen properly so that the power dissipation is minimized. when the voltage at pin pr equals v bat2 + 1 v + (50 w x i loop ), at least 98% of the loop current minus 2.5 ma flows into v bat2 and 2.5 ma + 2% of the loop current plus quiescent current flows into v bat1 . to choose v bat2 , add: 1. maximum tip overhead voltage (2 v for v ovh = 0). 2. maximum loop voltage (maximum loop resistance, protection resistance, and dc feed resistance [100 w ] times the maximum loop current limit). 3. 1 v for the soft switch. thus, for a 40 ma current limit, 640 w loop, 30 w pro- tection resistors, and 3.17 dbm signal (v ovh = 0): v bat2 = C(2 + 0.042 x (100 + 60 + 640) + 1) = C36.6 v then, for any loop resistance from 0 w to 640 w , the worst-case v bat1 and v bat2 currents will be: i bat1 = 1.39 ma + 2.5 ma + 0.02 x (42 ma C 2.5 ma) = 4.68 ma i bat2 = (0.98) x 42 ma = 38.71 ma total max power = 1.641 w (v bat = C48 v) note that to minimize power statistically, this may not be the best choice for v bat2 . over a large number of lines, power is minimized according to the statistical distribution of loop resistance. 12-3470a (f) figure 12. l9310 loop/battery current (with battery switch) vs. loop resistance v bat2 3.0 C i lim ----------------------------------- 0200 0.000 0.004 0.010 r loop ( w ) 400 battery/loop current (ma) 600 1000 800 0.016 i loopdc i bat1 i bat2 0.002 0.006 0.012 0.018 0.008 0.014 0.020 0.022 0.024 0.026 0.028 0.030
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 34 agere systems inc. applications (continued) dc characteristics (continued) power control resistor device temperature rise may be controlled with use of a single battery voltage by use of a power control resis- tor. this technique will reduce power dissipation on the chip, by sharing the total power not dissipated in the loop between the l9310 and the power control resistor. it does not, however, reduce the total power con- sumed, as does use of the auxiliary battery. the power control resistor is connected from the primary battery to the v bat2 /pwr node of the device. the magnitude of the power control resistor must be low enough to ensure that sufficient power is dissipated on the resistor to ensure the l9310 does not exceed its thermal shutdown temperature. at the same time, the more power that is dissipated by the power control resistor, the higher the resistors power rating must be, and thus, the more costly the resistor. the following equations are used to optimize the choice (magnitude and power rating) of the power control resistor. again assume: t tsd C t ambient(max) = allowed thermal rise 150 c C 85 c = 65 c allowed thermal rise = package thermal impedance x slic power dissipation 65 c = 38 c/w x slic power dissipation allowed slic power dissipation (p d ) = 1.71 w this time, assume a maximum ambient operating tem- perature of 85 c, a maximum current limit of 45 ma (including tolerance), and a maximum battery of C56 v. again, assume a (worst-case) minimum dc loop of 0 w and that 50 w protection resistors are used. assume the handset is 200 w : to ta l p d = (56 v x 45 ma) + 0.100 w to ta l p d = 2.34 w + 0.100 w to ta l p d = 2.4375 w again, the power dissipated in the slic is the total power dissipation less the power that is dissipated in the loop. slic p d = total power C loop power loop power = (i lim ) 2 x (r loopdcmin + 2r p + r handset ) loop power = (45 ma) 2 x (0 w + 100 w + 200 w ) loop power = 0.6075 w slic power = 2.4375 w C 0.6075 w slic power = 1.83 w > 1.5 w under these extreme conditions, thermal margin is increased via an external power control resistor. the power dissipated in the power control resistor is calculated by: p prw = where in this example: p prw is power in the resistor v bat = C52 v v loop = i lim * (r loop + r prot ) v roh is the ring-side overhead voltage of the slic. since this device is dc unbalanced, the tip side over- head will remain typically at C2 v and the ring side over- head will vary with the voltage at v oh . for the total tip/ ring default overhead of 5.5 v, the ring overhead is typi- cally 3.5 v. dc loop current limit in the active modes, dc current limit is programmable via an applied voltage source at the devices v prog control input. the voltage source may be an external voltage source or derived via a resistor divider network from the v ref slic output or an external voltage source. a programmable external voltage source may be used to provide software control of the loop current limit. the loop current limit (i lim ) is related to the v prog voltage by: i lim (ma) = 50 x v prog (v) v bat v roh C v loop C () 2 r pwr ----------------------------------------------------------------------
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 35 applications (continued) dc characteristics (continued) dc loop current limit (continued) note that the overall current-limit accuracy achieved will not only be affected by the specified accuracy of the internal slic current-limit circuit (accuracy associ- ated with the 50 term), but also by the accuracy of the voltage source and the accuracy of any external resis- tor divider network used and voltage offsets due to the specified input bias current. if a resistor divider from v ref is used, a lower magnitude resistor will give a more accurate result due to a lower offset associated with the input bias current; however, lower value resis- tors will also draw more power from v ref . the sum of the two resistors in the resistor divider should be between 75 k w and 200 k w . offset at v prog and v ref accuracies are specified in table 9 and table 10. the above equation describes the active mode steady- state current-limit response. there will be a transient response of the current-limit circuit (with the device in the active mode) upon an on- to off-hook transition. typical active mode transient current-limit response is given in table 18. table 18. typical active mode on- to off-hook tip/ ring current-limit transient response the current limit with the slic set in an active mode will be different from the current limit with the slic set in the scan mode. this is due to differences in the scan clamp circuit versus the active tip/ring drive amplifiers. the scan mode current limit is fixed and is a function of the internal design of the scan clamp circuit. the steady-state scan mode current limit will be a typical 40 ma to 50 ma and may, over temperature and pro- cess, vary typically from 30 ma to 110 ma. the scan clamp current limit will typically settle to its steady-state value within 300 ms. overhead voltage overhead is programmable in the active mode via an applied voltage source at the devices ovh control input. the voltage source may be an external voltage source or derived via a resistor divider network from the v ref slic output or an external voltage source. a programmable external voltage source may be used to provide software control of the overhead voltage. the overhead voltage (v oh ) is related to the ovh volt- age by: v oh = 5.5 v + 5 x v ovh (v) overall accuracy is determined by the accuracy of the voltage source and the accuracy of any external resis- tor divider network used and voltage offsets due to the specified input bias current. if a resistor divider from v ref is used, lower magnitude resistor will give a more accurate result due to a lower offset associated with the input bias current; however, lower value resistors will also draw more power from v ref . the sum of pro- gramming resistors should be between 75 k w and 200 k w . note that a default overhead voltage of 5.5 v is achieved by shorting input pin ovh to analog ground. internally, the slic needs typically 2 v from each sup- ply rail to bias the amplifier circuitry. this can be thought of as an internal saturation voltage. the default overhead provides sufficient headroom for on-hook transmission of a 3.14 dbm signal into 900 w . 3.14 = 10 log v = 1.36 v, which is required over and above the inter- nal saturation voltage for signal swing. 1.36 v + 4 v = 5.36 v < 5.5 v default overhead; thus, a 3.14 dbm into 900 w signal is passed without clipping distortion. the overhead voltage accuracy achieved will not only be affected by the accuracy of the internal slic cir- cuitry, but also by the accuracy of the voltage source and the accuracy of any external resistor divider net- work used. in the scan mode, overhead is unaffected by v ovh and internally fixed by the scan clamp circuitry to within the specified limits. parameter value unit dc loop current: active mode r loop = 100 w on- to off-hook transition t < 5 ms i lim + 60 ma dc loop current: active mode r loop = 100 w on- to off-hook transition t < 50 ms i lim + 20 ma dc loop current: active mode r loop = 100 w on- to off-hook transition t < 300 ms i lim ma v 2 0.9 -------- -
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 36 agere systems inc. applications (continued) dc characteristics (continued) overhead voltage (continued) the testsig and rcv inputs will not overload with an input signal swing betwen ground and v cc C 0.5 v. however, the slic output saturation point (at pt/pr) is a function of the device overhead. default overhead with ovh = 0 is 3.14 dbm into 900 w . after that, output signal swing increases 1 v for every volt that overhead is increased. overhead voltage may need to be increased to accom- modate on-hook transmission of higher-voltage sig- nals, such as meter pulse. the following example is meant to illustrate the design procedure that can be fol- lowed. assume that an on-hook transmission of a 2.2 vrms meter pulse into 200 w is needed. further assume 50 w protection resistors are used. v oh = 4.0 v + (1+ (2 x rp)/200) x vpeak v oh = 4.0 + (1+ (2 x 50)/200) x 2.2 (1.414) v oh = 8.662 v adding 0.5 v for tolerance, the overhead needs to be increased to (8.662 + 0.5) 9.16 ? 9.2 v to allow for an undistorted on-hook transmission of a 2.2 vrms meter pulse into 200 w . the overhead is set with respect to battery voltage and during a test mode, the battery voltage is unknown. with zero voltage on rcv input, the output is battery voltage minus the overhead on the input, which is the main offset. the small rcv input offset that is multi- plied by rcv gain to tip/ring output is inconsequential. loop range the dc loop range is calculated using: r l = C 2r p C r dc v bat1 is used because the maximum loop range is being calculated. the loop resistance value where the device automatically switches to v bat2 is calculated in the automatic battery switch section of this data sheet. battery feed the l9310 operates in a dc unbalanced mode. in the forward active state, under open circuit (on-hook) con- ditions, with the default overhead chosen, the tip to ring voltage will be a nominal 5.5 v less than the battery. this is the overhead voltage. the tip and ring overhead is achieved by biasing ring a nominal 3.5 v above bat- tery and by biasing tip a nominal 2.0 v below ground. during off-hook conditions, some dc resistance will be applied to the subscriber loop as a function of the phys- ical loop length, protection, and telephone handset. as the dc resistance decreases from infinity (on-hook) to some finite value (off-hook), the tip to ring voltage will decrease as shown in figure 13. 12-3431a (f) figure 13. tip/ring voltage as illustrated in figure 13, as loop length decreases, the tip to ground voltage will decrease with a slope cor- responding to one-half the internal dc feed resistance of the slic (typical 75 w ). the ring to ground voltage will also decrease with a slope corresponding to one- half the internal dc feed resistance of the slic, until the slic reaches the current-limit region of operation. at that point, the slope of the ring to ground voltage will increase to the sum of one half the internal dc feed resistance plus approximately 10 k w . the dc feed characteristic can be described by: i loop = v t/r = where: i loop = dc loop current. v t/r = dc loop voltage. ? v bat ? = battery voltage magnitude. v oh = overhead voltage. r loop = loop resistance, including wire and handset resistance. r p = protection resistance. r dc = slic internal dc feed resistance. refer to figure 13 and figure 14 in this section and to figure 12 in the automatic battery switch section. v bat v oh C i loop ---------------------------------- vtip to gnd (1/2)r dc begin current limiting (1/2)r dc (1/2)r dc + r lim decreasing loop length v bat vring to gnd v bat v oh C r loop 2r p r dc ++ ------------------------------------------------------ v bat v oh C () r loop r loop 2r p r dc ++ --------------------------------------------------------------- -
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 37 applications (continued) dc characteristics (continued) battery feed (continued) 12-3050.g (f) notes: v bat1 = C48 v. v bat2 = C24 v. i lim = 40 ma (r prog = 66.5 k w ). figure 14. l9310 loop current vs. loop voltage starting from the on-hook condition and going through to a short circuit, the curve passes through two regions: region 1: on-hook and low loop currents: the slope corresponds to the dc feed resistance of the slic (plus any series resistance). the open-circuit voltage is the battery voltage less the overhead voltage of the device. region 2: current limit: the dc current is limited to a value determined by v prog . this region of the dc tem- plate has a high resistance (10 k w ). notice that the i-v curve is uninterrupted when the power is shifted from the high-voltage battery to the low-voltage battery (if auxiliary battery option is used). this is shown in figure 12 in the automatic battery switch section. battery reversal rate the rate of battery reverse is controlled or ramped by capacitors fb1 and fb2. a chart showing fb1 and fb2 values versus typical ramp time is given below. leave fb1 and fb2 open if it is not desired to ramp the rate of battery reversal. table 19. fb1 and fb2 values vs. typical ramp time * typical recommended value for c fb1 and c fb2 is less than 0.033 m f. longitudinal to metallic balance longitudinal to metallic balance at pt/pr is specified in the electrical characteristics section of this data sheet. supervision loop closure loop closure supervision threshold is programmed via an applied voltage source or ground, through a resistor at the lcth input. loop closure status is presented at the nstat output. nstat is an unlatched output that represents either the loop closure or ring trip status, depending on the device state. see table 2 and table 3 for more details. loop closure threshold current (i lcth ) is set by: = i lcth (ma) where: r lcth is a resistor from the lcth node to ground or a voltage source. v lcth is ground or an external voltage source. there is a built-in hysteresis associated with the loop closure detector. the above equation describes the on- hook to off-hook threshold. to help prevent false glitches, the off-hook to on-hook threshold will be a typ- ical 20% lower than the corresponding on-hook to off- hook threshold.ppm injection can cause false loop clo- sure indication. connect a 0.01 m f capacitor to a 0.1 m f capacitor from this node, lcf to v cc to filter the loop closure detector the larger the capacitor the higher the filtering. if loop closure filtering is not required, leave lcf open. loop current (ma) 0 510 25 0 20 30 40 50 loop voltage (v) 15 20 10 1 r dc 30 45 35 40 1 10 k w c fb1 and c fb2 * transition time 0.01 m f 20 ms 0.1 m f 220 ms 0.22 m f 440 ms 0.47 m f 900 ms 1.0 m f 1.8 s 1.22 m f2.25 s 1.3 m f 2.5 s 1.4 m f 2.7 s 1.6 m f 3.2 s 250 v ref v lcth C () r lcth k w () -------------------------------------------------- -
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 38 agere systems inc. supervision (continued) ring trip ring trip is set by the value of rs1. the ring trip threshold at the ring trip inputs is 2.5 v minimum, 3.5 v maximum. a resistor value of 400 w , as shown in figure 4, will set the ring trip current threshold to 7.5 ma typical. ring trip is asserted upon entering the ringing mode until the second zero crossing of ringing. this is either a positive-going zero crossing (between C40 v and C30 v at C50 v v bat ) or a negative-going zero crossing (between C10 v and C20 v at C50 v v bat ). the different threshold for positive-going and negative-going zero crossings is the result of hysteresis of approximately 20 v. the act of turning on the switch may or may not produce a ringing zero crossing, therefore, there may be a delay of up to almost one cycle of ringing or 50 ms until nstat is high. ring trip will not be asserted unless the ring trip thresh- old is exceeded for two zero crossings. this is either a positive-going zero crossing (between C40 v and C30 v at C50 v v bat ) or a negative-going zero crossing (between C10 v and C20 v at C50 v v bat ). the different threshold for positive-going and negative-going zero crossings is the result of hysteresis of approximately 20 v. note that since the ringing voltage is monitored at rsw, one zero crossing can occur at switch turn-on depending on initial conditions. ring trip is asserted immediately if the ring trip input is 15 v 3 v. tip or ring ground detector in the ground key or ground start applications, a com- mon-mode current detector is used to indicate that either a tip or ring ground has occurred (ground key) or an off-hook has occurred (ground start). the detection threshold is set by connecting a resistor from icm to ground. 2350/r icm (k w ) = i th (ma) additionally, a filter capacitor across r icm will set the time constant of the detector. no hysteresis is associ- ated with this detector. switching behavior the solid-state ring relay in the l9310 device is able to provide either make-before-break or break-before- make timing with respect to switching into and out of the ring mode. if switching is done directly into and out of the ring mode, the design of the l9310 will give make-before-break switching with respect to both the ring and tip side switches. to achieve break-before- make switching, the user should, via software control, enter an intermediate all-off mode when switching into and out of the ring mode. the all-off state should be held a minimum of 8 ms. make-before-break operation the break switches are constructed from dmos tran- sistors. the tip side ring return is also a dmos transis- tor. because the on resistance of the break switches is less than the tip side ring return switch, the break switches are physically bigger. this implies a larger gate to source capacitance, with inherently slower switching speeds since it will take longer to charge or discharge the gate to source capacitance of the break switches (to change the state of the switch). the ring access switch is a pnpn type device. the pnpn device has inherently faster switching speeds than any of the dmos type switches. going from the active to ring mode, the smaller tip side ring return switch and the pnpn ring access switch will change states before the larger break switches. thus, the ring contacts are made before the line break switches are broken: make-before-break operation. going from the ring mode to active or scan, the natural tendency is for the smaller tip side ring return dmos to break or open, before the larger dmos can turn on. this would not be make-before-break operation on the tip side. thus, circuitry is added to speed up charging of the tip break switch, to speed up the turn on of that switch to give make-before-break operation on the tip side. on the ring side, going from the ring mode to the active or scan mode, the pnpn will not turn off until the ring current drops below the hold current of the pnpn device (which is typically 500 m a); this is effectively zero cur- rent for zero current turn off. this can take up to one- half cycle of ringing to occur. with this inherent delay in switching by the pnpn ring access switch, the break switches will make contact before the ring access switch breaks contact; so again, make-before-break switching is achieved.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 39 supervision (continued) make-before-break operation (continued) with the make-before-break switch, there will be a period of time (depending on ring signal frequency but measured in tens of microseconds) where all four switch contacts will be on. this means that the ring generator will be connected through the current-limited break switches to the input of the slic device. current will be limited by the break switch current limit, and this will not damage the slic. this current may, however, cause a false glitch at the nstat supervision output that will need to be digitally filtered. the board designer should consider any ramifications of this state on the overall system or ring generator and battery design. the major benefit of make-before-break switching is that it will minimize any impulse noise generated during ringing cadence. in many cases when operating the switch in the make-before-break mode, no special design to switch at zero current and voltage crossing is required. impulse noise generation when using solid- state relays is documented in the impulse noise and the l758x series of solid state switches application note. break-before-make operation to achieve break-before-make, use the logic control sequence device switching as shown below. table 20. break-before-make logic control sequence device switching the advantage of break-before-make operation is that it eliminates the current spike when the ring access relay changes state. the disadvantage is that it forces an all-off state. under inductive ringing loads, due to ldi/dt effects, may cause a reduction in the impulse noise performance compared to make-before-break switching. protection external protection an external overvoltage clamp is required to ensure that the off-state and on-state ratings of the solid-state break switch and solid-state ring access switch are not exceeded. the solid-state switches in the l9310 are constructed in a dielectrically isolated high-voltage technology. because of the high device-to-device isola- tion that is inherent in the dielectric isolation, only a tip to ground and a ring to ground clamp is required. a tip to ring overvoltage clamp is not needed. a foldback or crowbar type device is recommended to minimize power across the solid-state switches under a fault condition. the break switches and tip return switch are con- structed from dmos transistors. because the on resis- tance of the break switches is less than the tip side ring return switch, the break switches are physically bigger and have a higher current handling capability. addition- ally, the break switches have a foldback characteristic which enables them to survive a higher on-state volt- age (320 v) than the tip ring return switch (130 v), which does not have the foldback characteristic. (see the on-state switch i-v characteristics section.) the ring access switch is a pnpn type device. additionally, the ring side will see the full power ring voltage, and the tip side switch will see the power ringing voltage that is attenuated by the ringing load, subscriber loop, feed resistor, and protection resistors. because of these dif- ferences, the protection requirements on the tip side are different from the protection requirements on the ring side. thus, it is recommended that an asymmetri- cal (with respect to tip and ring) overvoltage protection scheme be used. please contact your agere account representative for a recommended protection device. additionally, a series protection resistor with a fusible characteristic or a ptc resistor is recommended to limit current during lightning and power cross faults. a minimum 50 w is recommended in tip and ring. state break switches ring switches comment active/scan closed open disconnect (all-off) open open hold >8 ms ring open closed disconnect (all-off) open open hold >8 ms active/scan closed open
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 40 agere systems inc. protection (continued) external protection (continued) the overall device protection is achieved through a combination of the external overvoltage and overcur- rent devices, along with the integrated thermal shut- down feature, the integrated window comparator, the break switch foldback characteristic, and the dc/dynamic current-limit response of the break and tip return switches. active mode response at pt/pr the line break switches and tip return switch are cur- rent-limited switches. the current-limit mechanism lim- its current through the switch to the specified dc current limit under low frequency or dc faults (power cross and/or tip-ring to ground short) and limits the current to the specified dynamic current-limit response under transient faults, such as lightning. during a lightning fault (typical 1000 v 10 x 700 m s applied surge), the current-limited line break switches will pass typically 2.5 a for 0.5 m s before forcing the break switches off. once in the off state, the external protection device must ensure that the off-state voltage rating of 320 v is not exceeded. note that the maxi- mum differential voltage is the positive zener rating of the protection device less the battery voltage, which will appear on the line feed side of the switch. for a lower-voltage power cross, whose maximum peak voltage is below the foldback voltage breakpoint 1 (v1), the current-limited break switch will pass the cur- rent equal to the dc current limit. the current limit has a negative temperate coefficient, so as the device contin- ues to pass current, the current limit will reduce with increasing device temperature. ultimately, the device will reach the thermal shutdown temperature and the thermal shutdown mechanism will force an all-off state, which will stop current flow and begin device cooling. in the all-off state, the external protection device ensures that the switch off-state voltage rating is not exceeded. once the device cools significantly, the break switches will turn on, and current will begin to flow again, until temperature forces the all-off state. this will continue until the fault condition is gone. sneak-under surge is a voltage surge that is just below the clamping threshold of the secondary protection device. for this type of surge, when the surge voltage is below the foldback voltage breakpoint 1, operation is as described above. when the surge voltage rises above the foldback voltage breakpoint 1 (v1), but is still less than the secondary protector clamping voltage, the line break switch will crowbar into the high-impedance region of its i-v characteristic and reduce current to the specified i limit 2 value. for surges whose magnitude range above the trigger of the external secondary protector, the device will operate as described above for the portion of the surge below the secondary protector trigger voltage. when the voltage rises above the external secondary protec- tors trigger voltage, the secondary protector will crow- bar on, shunting fault current to ground and reducing the tip/ring voltage seen at the device. in the active mode, the external secondary protector must ensure that the off-state voltage ratings of the ring access and ring return switch are not exceeded. nor- mally, the ring return switch is connected to ground on the tring side and to the protector on the pt side; thus, the protector on the tip side in the active mode must clamp at less than 320 v. as will be seen in the ring mode response at pt/pr section, during the power ringing mode, this clamp voltage on the tip side is significantly less than 320 v. normally, the ring access switch is connected to the ring generator on the rring side and to the protector on the pr side; thus, on one side of the switch, there is the battery voltage and the peak negative ring signal, and on the pr side, the maximum turn-on voltage of the secondary protector. the ring access switch is of pnpn construction. thus, if the off-state voltage rating of the ring access switch is exceeded, the device will crowbar into a low-impedance state. this will cause a surge into the ring generator and can cause the on- state current rating of the switch to be exceeded. the difference of the battery plus peak negative ring signal voltage less the maximum turn on of the second- ary protector must not exceed the off-state voltage rat- ing of the ring access switch. additionally, as the secondary protector will see the power ring signal, the minimum turn-on rating of the secondary protector must be high enough to not clamp the ring signal and cause clipping distortion. the ring side will see the full power ring voltage, and the tip side switch will see the power ringing voltage that is attenuated by the ringing load, subscriber loop, feed resistor, and protection resistors; thus, the ring side secondary protector requires a higher clamping voltage than the tip side.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 41 protection (continued) ring mode response at pt/pr in this mode, the line break switches are off and the ring access and ring return switch is on. the secondary protectors must ensure that the minimum off-state volt- age rating of the line break switches is not exceeded. note that the maximum differential voltage is the posi- tive zener rating of the protection device less the bat- tery voltage which will appear on the line feed side of the switch. the ring access switch is a pnpn type switch. this switch has no internal current limiting. thus, through external current limit, the user must ensure that the surge ratings (both dynamic and dc for lightning and power cross faults) are not exceeded. a minimum 400 w ring feed resistor is recommended. this resistor also will set the ring trip threshold. see the ring trip section within the supervision section of this data s heet. during a lightning fault (typical 1000 v 10 x 700 m s applied surge), the current-limited tip return switch will pass, typically 2.5 a for 0.5 m s before forcing the switch off. once in the off state, the external protection device must ensure that the off-state voltage rating of 320 v is not exceeded. for power cross for lower-voltage faults, the tip side power ringing return switch will behave like the line break switches. however, this switch does not have the foldback clamping feature that is included in the line break switches; thus, in the on state, the voltage seen by the tip side power ringing return switch before dam- age is less than the line break switches. the on-state voltage of the line break switches can go up to the off- state voltage rating. the tip side power ringing return voltage should see less than 130 v in the on state. thus, the secondary protector on the tip side should have a maximum crowbar voltage of 130 v. with typical protection device tolerance, this implies a minimum clamping voltage of 100 v. the users should ensure, based on minimum loop length, ringing load, and peak ring signal voltage, that the ring signal is not distorted by the (lower) voltage rating of the tip-side protector. internal tertiary protection the external secondary protector and switch current limit protect the 320 v high-voltage switches from light- ning and power cross conditions. integrated into the lilac ic is an internal tertiary protection scheme that is meant to protect the 90 v slic portion of the device from residue fault current and voltages that may be passed through the switches to the actual slic inputs. this scheme includes an internal diode bridge voltage clamp and a battery out of range detector that forces an all-off condition if the battery voltage falls high or low out of the specified operating range. diode bridge the internal inputs of the actual slic chip are clamped to ground and to v bat1 by an integrated diode bridge. residual positive fault currents are clamped to ground and residual negative fault currents are clamped to bat- tery. this implies that the battery have some current- sinking capability. high common-mode currents, as may be seen under a fault condition, will be sensed and reduced to zero by the battery monitor circuit (see battery out of range detector: high [magnitude] section). however, this detector will not prevent longitudinal current from flow- ing into battery. the battery supply must have the abil- ity to sink longitudinal currents as specified in the longitudinal current capability requirement in table 10. battery out of range detector: high (magnitude) this feature is useful in remote power applications where a dc-dc converter with limited ability to sink cur- rent is used as the primary battery supply. under a fault condition, the diode bridge will want to sink current into the battery. as a function of the dc-dc converter input capacitance and design, this current may cause the magnitude of supply voltage to rise and ultimately cause damage to the supply. to prevent damage to the supply, the lilac device will monitor the battery supply voltage. if the magnitude of the battery rises above the maximum specified operating battery, the battery out of range detector will force the line break switches and ring access switches into an all-off state, and will also force the slic into the disconnect state. this will stop the current flow into the battery, preventing damage to the battery fault conditions. nstat is forced low during this mode of operation. battery out of range detector: low (magnitude) the lilac device will monitor the battery supply volt- age. if the magnitude of the battery drops below the minimum specified operating battery, the battery out of range detector will force the line break switches and ring access switches into an all-off state, and will also force the slic into the disconnect state. nstat is forced low during this mode of operation.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 42 agere systems inc. special functions periodic pulse metering (ppm) periodic pulse metering (ppm), also referred to as ttx, is input to the ppmin input of the l9310. upon application of appropriate logic control, this signal is presented to the tip/ring subscriber loop. the state of the l9310 may be changed while applying ppm sig- nals. the l9310 assumes that a shaped ppm signal is applied to the ppmin input. sufficient drive current is available in the tip and ring drive amplifiers to support 2.5 vrms ppm signals into a 200 w load with a 70 ma dc current limit, and a 5 vrms ppm signal into a 200 w load with a 45 ma dc current limit. ppm input signals may be a maximum 1.25 v at ppmin. the gain from ppmin to tip/ring is 10. thus, for 2.5 vrms at tip and ring, apply a 0.25 vrms signal at ppmin. the ppm signal should be ac coupled to ppmin through a 0.01 m f capacitor. when applied to tip and ring, the ppm signal will also be returned through the slic and will appear at the slic vitr output. the concern is that this high-voltage signal can overload the codec input and cause distor- tion of the (desired) ac signal. therefore, some sort of ppm rejection scheme must be employed. refer to figure 1, architecture diagram. the l9310 outputs pin ppmout, which is the output of the ppm input ampli- fier. connecting a resistor, r ppm, from ppmout to node itr will provide a path for a hybrid reject of the returned meter pulse signal. the return path from tip and ring to vitr for the ppm signal is through the internal ax amplifier. itr is the input to this amplifier. through r ppm , by applying a ppm signal equal in mag- nitude, but 180 degrees out of phase to the returned ppm signal at itr, the ppm signal is cancelled, pre- venting overload at the codec input. even if the cancel- lation is not perfect, the idea is to reduce the ppm signal so as not to overload the codec. codecs typi- cally have a low-pass filter at their input to reject any residual meter pulse signal. the value of r ppm is selected by: r ppm = [{(vppmin x 10)/(r ppmload + r dc + 2r p )}/324.5] C1 in the case of very high meter pulse signals, such as 5 vrms, the cancellation provided by resistor r ppm may not be sufficient to prevent overload at the codec input. in this case, additional filtering/rejection may be neces- sary. ppm injection can cause false loop closure indication. connect a 0.01 m f capacitor from this node lcf to v cc to filter the loop closure detector. if loop closure filtering is not required, leave lcf open. line test the l9310 provides line test capability. through a series of integrated analog switches, in the test mode, an analog voltage proportional to the dc tip to ground voltage, dc ring to ground voltage, the differential dc tip to ring voltage may be generated at the slic testlev output. additionally, an analog voltage pro- portional to the dc tip to ground current, dc ring to ground current, the differential dc tip to ring current may also be generated at the slic testlev. figure 2 shows the architecture of the integrated test switches. the test switches are configured via the logic input table to provide voltage measurements, tip to ground, ring to ground, and tip to ring. a voltage that is proportional to the ac tip/ring current appears at the vitr output; thus, for ac current measurements, the test switches apply the vitr output to the testlev output. a voltage that is proportional to the ac plus dc tip/ring current appears at the vtx output; thus, for dc current measurements, the test switches apply the vtx output to the testlev output, with testsig input grounded. differential tip to ring current is achieved via the logic truth table. additionally, individual control of the line break switches allows tip to ground current measure- ments (tip break switch closed, ring break switch open, tip amp state) or ring to ground current measurements (tip break switch open, ring break switch closed, ring amp state). an analog ac test tone may also be applied to a test input testsig. testsig input is active upon entering a test state and remains active until leaving the test mode. using this feature, a voltage proportional to ac tip to ground voltage, ac ring to ground voltage, the dif- ferential ac tip to ring, the ac tip to ground current, ac ring to ground current, the differential ac tip to ring cur- rent may also be generated at the slic testlev. by varying the frequency of the applied test tone, parame- ters such as line capacitance may be measured. if the codec can accommodate self-test features, the l9310 can be configured to operate in this mode. dur- ing the test modes, the l9310 receive path is active; thus, a test tone may be applied at the rcvn/rcvp inputs, through the codec, via a pcm input. in this mode of operation, couple testlev, not vitr, to the codec.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 43 special functions (continued) line test (continued) all measurements that appear at the testlev output are referenced to the internal v ref voltage of the device. for that reason, there is a test mode in which v ref itself will appear at the testlev output. when making a voltage measurement, first measure v ref and subtract v ref from v testlev . when making a current measurement, open the line break switches and measure v testlev . this value is then subtracted from the v testlev that is seen during the actual measurement. note that due to internal bias- ing of the line break switches, the value seen at v testlev with the line break switches open will be less than the value seen with the line break switches closed under on-hook (open-loop) conditions. testsig should be externally connected to the device's v ref if it is not used during a test condition. this may be done by a high-impedance pull-up resis- tor. additionally, testsig should be ac coupled to the test signal generator. table 21 shows design equations to measure the vari- ous line voltages and currents. table 21. testlev output options test mode relationship comments test off high impedance v ref v testlev = v ref + v offset unity follower on v ref . this is the voltage measurement calibration state, use the v ref state in the secondary control state table. tip-to-ring voltage (v tip C v ring ) = 75 (1 C 0.0075 |v tl |) x v tl v tl = v testlev C (v ref + v offset ) difference amp. tip-to-ground volt- age v tip = C75 (1 C 0.0075 |v tl |) x v tl + v ref + v offset v tl = v testlev C (v ref + v offset ) inverting amp. ring-to-ground volt- age v ring = C75 (1 C 0.0075 |v tl |) x v tl + v ref + v offset v tl = v testlev C (v ref + v offset ) inverting amp. vtx, zero current (tip open, ring open) v testlev = v zerocur unity follower on vtx close to v ref + v axoffset + v off- set . this is the current measurement calibration state. in the secondary control state table, use tip amp or ring amp for single-ended current measurement calibration. use tip and ring amp for differential current measure- ment calibration. do not use the disconnect mode for current calibration. vtx, dc current tip/ ring (tip closed, ring closed) v testlev = 20 v/a x i tip-to-ring + v zerocur differential current. vtx, dc current ring ground (tip closed, ring open) v testlev = 10 v/a x i tip-to-ring + v zerocur single-ended voltage. vtx, dc current ring ground (tip open, ring closed) v testlev = C10 v/a x i tip-to-ring + v zerocur single-ended voltage. vitr, zero current (tip open, ring open) v testlev = v zac unbuffered output of vitr close to v ref + v axoffset + v acoffset . this is the current measurement calibration state. in the secondary control state table, use tip amp or ring amp; for single-ended current measurement calibra- tion, use tip and ring amp for differential current mea- surement calibration. do not use the disconnect mode for current calibration. vitr, ac current (tip closed, ring closed) v testlev = 300 v/a x i tip-to-ring + v zac
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 44 agere systems inc. ac applications ac parameters there are four key ac design parameters. termination impedance is the impedance looking into the 2-wire port of the line card. it is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. transmit gain is measured from the 2-wire port to the pcm highway, while receive gain is done from the pcm highway to the transmit port. transmit and receive gains may be specified in terms of an actual gain, or in terms of a transmission level point (tlp), that is, the actual ac transmission level in dbm. finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. codec types at this point in the design, the codec needs to be selected. the interface network between the slic and codec can then be designed. below is a brief codec feature summary. first-generation codecs. these perform the basic filtering, a/d (transmit), d/a (receive), and m -law/a-law companding. they all have an op amp in front of the a/d converter for transmit gain setting and hybrid bal- ance (cancellation at the summing node). depending on the type, some have differential analog input stages, differential analog output stages, +5 v only or 5 v operation, and m -law/a-law selectability. these are available in single and quad designs. this type of codec requires continuous time analog filtering via external resistor/capacitor networks to set the ac design parameters. an example of this type of codec is the agere t7504 quad 5 v only codec. this type of codec tends to be the most economical in terms of piece part price, but tends to require more external components than a third-generation codec. further ac parameters are fixed by the external r/c network so software control of ac parameters is diffi- cult. third-generation codecs. this class of devices includes all ac parameters set digitally under micropro- cessor control. depending on the device, it may or may not have data control latches. additional functionality sometimes offered includes tone plant generation and reception, ppm generation, test algorithms, and echo cancellation. again, this type of codec may be +5 v only or 5 v operation, single quad or 16-channel, and m -law/a-law or 16-bit linear coding selectable. exam- ples of this type of codec are the agere t8536/7 (5 v only, quad, standard features), t8533/4 (5 v only, quad with echo cancellation), and t8531/36 (5 v only, 16- channel with self-test). ac interface network the ac interface network between the l9310 and the codec will vary depending on the codec selected. with a first-generation codec, the interface between the l9310 and codec actually sets the ac parameters. with a third-generation codec, all ac parameters are set dig- itally, internal to the codec; thus, the interface between the l9310 and this type of codec is designed to avoid overload at the codec input in the transmit direction, and to optimize signal to noise ratio (s/n) in the receive direction. because the design requirements are very different with a first- or third-generation codec, the l9310 is offered with two different receive gains. each receive gain was chosen to optimize, in terms of external com- ponents required, the ac interface between the l9310 and codec. with a first-generation codec, the termination imped- ance is set by providing gain shaping through a feed- back network from the slic vitr output to the slic rcvn/rcvp inputs. the l9310 provides a transcon- ductance from t/r to vitr in the transmit direction and a single-ended to differential gain in the receive direc- tion from either rcvn or rcvp to t/r. assuming a short from vitr to rcvn or rcvp, the maximum impedance that is seen looking into the slic is the product of the slic transconductance times the slic receive gain, plus the protection resistors. the various specified termination impedance can range over the voiceband as low as 300 w up to over 1000 w . thus, if the slic gains are too low, it will be impossible to syn- thesize the higher termination impedances. further, the termination that is achieved will be far less than what is calculated by assuming a short for slic output to slic input. in the receive direction, in order to control echo, the gain is typically a loss, which requires a loss net- work at the slic rcvn/rcvp inputs, which will reduce the amount of gain that is available for termina- tion impedance. for this reason, a high-gain slic is required with a first-generation codec.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 45 ac applications (continued) ac interface network (continued) with a third-generation codec, the line card designer has different concerns. to design the ac interface, the designer must first decide upon all termination imped- ance, hybrid balances, and tlp requirements that the line card must meet. in the transmit direction, the only concern is that the slic does not provide a signal that is too large and overloads the codec input. thus, for the highest tlp that is being designed to, given the slic gain, the designer, as a function of voice band frequency, must ensure the codec is not overloaded. with a given tlp and a given slic gain, if the signal will cause a codec overload, the designer must insert some sort of loss, typically a resistor divider, between the slic output and codec input. in the receive direction, the issue is to optimize the s/n. again, the designer must consider all the consid- ered tlps. the idea, for all desired tlps, is to run the codec at or as close as possible to its maximum output signal, to optimize the s/n. remember, noise floor is constant, so the larger the signal from the codec, the better the s/n. the problem is if the codec is feeding a high-gain slic, either an external resistor divider is needed to knock the gain down to meet the tlp requirements, or the codec is not operated near maxi- mum signal levels, thus compromising the s/n. thus, it appears the solution is to have a slic with a low gain, especially in the receive direction. this will allow the codec to operate near its maximum output signal (to optimize s/n), without an external resistor divider (to minimize cost). note also that some third-generation codecs require the designer to provide an inherent resistive termina- tion via external networks. the codec will then provide gain shaping, as a function of frequency, to meet the return loss requirements. further stability issues may add external components or excessive ground plane requirements to the design. to meet the unique requirements of both types of codecs, the l9310 offers two receive gain choices. these receive gains are mask programmable at the factory and are offered as two different code variations. for interface with a first-generation codec, the l9310 is offered with a receive gain of 8. for interface with a third-generation codec, the l9310 is offered with a receive gain of 2. in either case, the transconductance in the transmit direction, or the transmit gain, is 300 w . this selection of receive gain gives the designer the flexibility to maximize performance and minimize exter- nal components, regardless of the type of codec cho- sen. design tools the following examples illustrate the design tech- niques/equations followed to design the ac interface with a first- or third-generation codec for both a resis- tive and complex design. to aid the line circuit design, agere has available windows *-based spreadsheets to do the individual component calculations. further, agere has available pspice ? models for circuit simula- tion and verification. consult your agere account rep- resentative to obtain these design tools. first-generation codec ac interface network termination impedance may be specified as purely resistive or complex, that is, some combination of resistors and capacitors that causes the impedance to vary with frequency. the design for a pure resistive ter- mination, such as 600 w , does not vary with frequency, so it is somewhat more straightforward than a complex termination design. for this reason, the case of a resis- tive design and complex design will be shown sepa- rately. * windows is a registered trademark of microsoft corporation. ? pspice is a registered trademark of microsim corporation.
46 data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 46 agere systems inc. first-generation codec ac interface net- work: resistive termination the following reference circuit shows the complete slic schematic for interface to the agere t7504 first- generation codec for a resistive termination imped- ance. for this example, the ac interface was designed for a 600 w resistive termination and hybrid balance with transmit gain and receive gain set to 0 dbm. for illustration purposes, no ppm injection was assumed in this example. this implies use of the default overhead voltage and no components for meter pulse rejection. also, this example illustrates the device with a single battery operation and fixed overhead, current limit, and loop closure threshold. this is a lower feature applica- tion example. resistor r gn is optional. it compensates for any mis- match of input bias voltage at the rcvn/rcvp inputs. if it is not used, there may be a slight offset at tip and ring due to mismatch of input bias voltage at the rcvn/rcvp inputs. it is very common to simply tie rcvn directly to ground in this particular mode of oper- ation. if used, to calculate r gn , the impedance from rcvn to ac ground should equal the impedance from rcvp to ac ground. 12-3580b (f) figure 15. ac equivalent circuit r p z t + C r p v t/r i t/r v s z t/r + C ring a v = C1 a v = 1 vitr current sense tip + C r t3 r rcv r hb1 r t6 rcvn rcvp r x vgsx vf x in vfr 1/4 t7504 codec r gp 2.4 v C0.300 v/ma a v = 4 l9310 vf x ip 18 w 18 w 20 w 20 w break switch break switch v ref v ref
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 47 ac applications (continued) first-generation codec ac interface network: resistive termination (continued) example 1, real termination the following design equations refer to the circuit in figure 15. use these to synthesize real termination imped- ance. termination impedance: z t = receive gain: transmit gain: hybrid balance: h bal = 20 log h bal = 20 log to optimize the hybrid balance, the sum of the currents at the vfx input of the codec op amp should be set to 0. the expression for zhb becomes: v t/r i t/r C ------------ z t 76 w 2 + r p 2400 1 r t3 r gp -------- - r t3 r rcv ----------- - ++ ----------------------------------- + = g rcv v t/r v fr ----------- - = g rcv 8 1 r rcv r t3 ----------- r rcv r gp ----------- - ++ ? ?? 1 z t z t/r -------- - + ? ?? ------------------------------------------------------------------ = g tx v gsx v t/r ---------- - = g tx r x C r t6 -------- - 300 z t/r -------- - = r x r hb1 -------------- - g tx C g rcv ? ?? v gsx v fr -------------- - ? ?? r hb k w () r x g tx g rcv ------------------- =
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 48 agere systems inc. ac applications (continued) first-generation codec ac interface network: resistive termination (continued) example 1, real termination (continued) 12-3521g (f) notes: termination impedance = 600 w. hybrid balance = 600 w. tx = 0 dbm. rx = 0 dbm. figure 16. agere t7504 first-generation codec resistive termination, nonmeter pulse application, single battery operation r g1 fusible 50 w c vbat1 0.1 m f v bat1 rcvn rts l9310 ovh (default overhead) v prog (i limit = 40 ma) v bat fb2 c f2 0.015 m f lcf cf1 vtx rcvp r t3 140 k w r rcv 100 k w r hb1 100 k w vfxin r x 100 k w gsx v fro dx dr fse fsep mclk asel 1/4 t7504 codec control inputs pcm highway sync and clock C + itr ppmout c rti 0.1 m f ppmin agnd v dd +2.4 v c c2 0.1 m f r gn r gp 43.2 k w 1 m w 50 w r ring t ring 100 v130 v secondary or ptc fusible or ptc r rtf 400 w ringing source c cc 0.1 m f v cc c dd 0.1 m f v dd ad c tx 0.15 m f r gx 6.34 k w c c1 0.33 m f r t6 49.9 k w rsw pt pwr v bat2 /v cc bgnd v bat1 trgdet icm dgnd txi txn vitr protector 180 v330 v secondary protector v ref b3 fb1 b2 b1 b0 v ref testlev testsig cf2 multiplexed data bus to/from microprocessor per-line to/from microprocessor pr (gain of 8) nstat reset latch 28.3 k w r vprog 33.2 k w r vref 64.9 k w r lcth 59 k w lcth (10 ma) v ref v ref
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 49 ac applications (continued) first-generation codec ac interface network: resistive termination (continued) example 1, real termination (continued) table 22 . l9310 parts list for agere t7504 first-generation codec resistive termination, nonmeter pulse application, single battery operation * see your agere account representative for a recommended secondary protection device. name value tolerance rating function fault protection r pr 50 w 1% fusible or ptc protection resistor. r pt 50 w 1% fusible or ptc protection resistor. protector* 180 v to 320 v ring-side secondary protector. protector* 100 v to 130 v tip-side secondary protector. power supply c vbat1 0.1 m f 20% 100 v filter capacitor. c cc 0.1 m f 20% 10 v filter capacitor. c dd 0.1 m f 20% 10 v filter capacitor. c f2 0.015 m f 20% 100 v filter capacitor. dc profile r vprog 33.2 k w 1% 1/16 w with r vref fix dc current limit. r vref 64.9 k w 1% 1/16 w with r vprog fix dc current limit. supervision c rtf 0.1 m f 20% 100 v ring trip filter capacitor. r rtf 1 m w 1% 1/16 w ring trip filter resistor. r rs1 400 w 5% 2 w sets ring trip threshold. r lcth 59 k w 1% 1/16 w with r vref , fix loop supervision threshold. ac interface r gx 6.34 k w 1% 1/16 w sets t/r to vitr transconductance. c tx 0.15 m f 20% 10 v ac/dc separation. c c1 0.33 m f 20% 10 v dc blocking capacitor. c c2 0.1 m f 20% 10 v dc blocking capacitor. r t3 140 k w 1% 1/16 w with r gp and r rcv , sets termination impedance and receive gain. r t6 49.9 k w 1% 1/16 w with r x , sets transmit gain. r x 100 k w 1% 1/16 w with r t6 , sets transmit gain. r hb 100 k w 1% 1/16 w with r x , sets hybrid balance. r rcv 100 k w 1% 1/16 w with r gp and r t3 , sets termination impedance and receive gain. r gp 43.2 k w 1% 1/16 w with r rcv and r t3 , sets termination impedance and receive gain. r gn optional 28.3 k w 1% 1/16 w optional. compensates for input offset at rcvn/rcvp.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 50 agere systems inc. ac applications (continued) first-generation codec ac interface net- work: complex termination the following reference circuit shows the complete slic schematic for interface to the agere t7504 first- generation codec for the german complex termination impedance. for this example, the ac interface was designed for a 220 w + (820 w || 115 nf) complex ter- mination and hybrid balance with transmit gain and receive gain set to 0 dbm. for illustration purposes, 2.2 vrms ppm injection was assumed in this example. this implies the overhead voltage is increased to 9.2 v and hybrid meter pulse rejection is used. also, this example illustrates the device using the battery switch with multiple battery operation and fixed overhead, cur- rent limit, and loop closure threshold. complex termination impedance design complex termination is specified in the form: 5-6396(f) to work with this application, convert termination to the form: 5-6398(f) where: r 1 = r 1 + r 2 r 2 = (r 1 + r 2 ) c = c ac interface using first-generation codec r tgp /r tgs /c gs (z tg ): these components give gain shaping to get good gain flatness. these components are a scaled version of the specified complex termina- tion impedance. note that for pure (600 w ) resistive terminations, com- ponents r tgs and c gs are not used. resistor r tgp is used and is still 6.34 k w . r x /r t6 : with other components set, the transmit gain (for complex and resistive terminations) r x and r t6 are varied to give specified transmit gain. r t3 /r rcv /r gp : for both complex and resistive termina- tions, the ratio of these resistors set the receive gain. for resistive terminations, the ratio of these resistors sets the return loss characteristic. for complex termi- nations, the ratio of these resistors set the low-fre- quency return loss characteristic. c n /r n1 /r n2 : for complex terminations, these compo- nents provide high-frequency compensation to the return loss characteristic. for resistive terminations, these components are not used and rcvn is connected to ground via a resistor. r hb : sets hybrid balance for all terminations. set z tg gain shaping z tg = r tgp || r tgs + c gs , which is a scaled version of z t/r (the specified termination resistance), in the r 1 || r 2 + c form. r tgp must be 6.34 k w to set slic transconductance to 300 v/a. r tgp = 6.34 k w at dc, c gs and c are open. r tgp = m x r 1 where m is the scale factor. m = it can be shown: r tgs = m x r 2 and c tgs = r 2 c r 1 r 1 c r 2 r 1 r 2 ------- r 2 r 1 r 2 + --------------------- ? ?? 2 6340 r 1 -------------- c m ------
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 51 ac applications (continued) first-generation codec ac interface network: complex termination (continued) 5-6400.m (f) figure 17. interface circuit using first-generation codec (blocking capacitors not shown) 0.1 m f r tgs v tx r tgp = 6.34 k w t xi v itr r t6 r x r t3 r hb codec output drive amp codec op amp C + 15 c n r n1 r n2 r gp r rcv rcvn rcvp Ci t/r 324.5 c g v ref v ref transmit gain transmit gain will be specified as a gain from t/r to pcm, t x (db). since pcm is referenced to 600 w and assumed to be 0 db, and in the case of t/r being refer- enced to some complex impedance other than 600 w resistive, the effects of the impedance transformation must be taken into account. again, specified complex termination impedance at t/r is of the form: 5-6396(f) first, calculate the equivalent resistance of this network at the midband frequency of 1000 hz. r eq = using r eq , calculate the desired transmit gain, taking into account the impedance transformation: t x (db) = t x (specified[db]) + 20 log t x (specified[db]) is the specified transmit gain. 600 w is the impedance at the pcm and r eq is the impedance at tip and ring. 20 log represents the power loss/gain due to the impedance transformation. note in the case of a 600 w pure resistive termination at t/r 20 log = 20 log = 0. thus, there is no power loss/gain due to impedance transformation and t x (db) = t x (specified[db]) . finally, convert t x (db) to a ratio, g tx : t x (db) = 20 log g tx the ratio of r x /r t6 is used to set the transmit gain: = g tx ? ? with a quad agere codec such as t7504: r x < 200 k w r 2 c r 1 2 p f () 2 c 2 r 1 r 2 2 r 1 r 2 ++ 12 p f () 2 r 2 2 c 2 + -------------------------------------------------------------------------- ? ? ?? 2 2 p f r 2 2 c 12 p f () 2 r 2 2 c 2 + ----------------------------------------------- - ? ? ?? 2 + 600 r eq ---------- - 600 r eq ---------- - 600 r eq ---------- - 600 600 --------- - r x r t6 ---------- 324.5 15 -------------- - 1 m ---- -
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 52 agere systems inc. ac applications (continued) first-generation codec ac interface net- work: complex termination (continued) receive gain ratios of r rcv , r t3 , r gp will set both the low-frequency termination and receive gain for the complex case. in the complex case, additional high-frequency compen- sation, via c n , r n1 , and r n2 , is needed for the return loss characteristic. for resistive termination, c n , r n1 , and r n2 are not used and rcvn is tied to ground via a resistor. determine the receive gain, g rcv , taking into account the impedance transformation in a manner similar to transmit gain. r x (db) = r x (specified[db]) + 20 log r x (db) = 20 log g rcv then: g rcv = and low-frequency termination z ter(low) = + 2r p + 76 w z ter(low) is the specified termination impedance assum- ing low frequency (c or c is open). r p is the series protection resistor. these two equations are best solved using a computer spreadsheet. next, solve for the high-frequency return loss compen- sation circuit, c n , r n1 , and r n2 : c n r n2 = c g r tgp r n1 = r n2 there is an input offset voltage associated with nodes rcvn and rcvp. to minimize the effect of mismatch of this voltage at t/r, the equivalent resistance to ac ground at rcvn should be approximately equal to that at rcvp. hybrid balance set the hybrid cancellation via r hb . r hb = r eq 600 ---------- - 4 1 r rcv r t3 --------------- r rcv r gp --------------- ++ ----------------------------------------------- - 2400 1 r t3 r gp ----------- - r t3 r rcv --------------- ++ -------------------------------------------- 2r p 76 w + () 2400 ---------------------------------- 2400 2r p 76 w + () ---------------------------------- r tgs r tgp ------------- - ? ?? 1 C r x g rcv g tx ------------------------------ -
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 53 ac applications (continued) first-generation codec ac interface network: complex termination (continued) blocking capacitors 5-6401.k (f) figure 18. ac interface using first-generation codec (including blocking capacitors) for complex termination impedance 0.1 m f r tgs v tx r tgp = 6.34 k w t xi v itr r t6 r x r t3 r hb codec output drive amp codec op amp C + 15 c n r n1 r n2 r gp r rcv rcvn rcvp Ci t/r 324.5 c gs c b1 2.5 v c b2 v ref v ref if a 5 v only codec such as the agere t7504 is used, dc blocking capacitors must be added as shown in fig- ure 18. this is because the codec is referenced to 2.5 v and the slic to groundwith the ac coupling, a dc bias at t/r is eliminated and power associated with this bias is not consumed. typically, values of 0.1 f to 0.47 f capacitors are used for dc blocking. the addition of blocking capaci- tors will cause a shift in the return loss and hybrid bal- ance frequency response toward higher frequencies, degrading the lower-frequency response. the lower the value of the blocking capacitor, the more pro- nounced the effect is, but the cost of the capacitor is lower. it may be necessary to scale resistor values higher to compensate for the low-frequency response. this effect is best evaluated via simulation. a pspice model for the l9310 is available. design equation calculations seldom yield standard component values. conversion from the calculated value to standard value may have an effect on the ac parameters. this effect should be evaluated and opti- mized via simulation.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 54 agere systems inc. ac applications (continued) first-generation codec ac interface network: complex termination (continued) basic loop start application using t7504 type codec 12-3528b (f) notes: termination impedance = 220 w + (820 w || 115 nf). hybrid balance = 220 w + (820 w || 115 nf). tx = 0 dbm. rx = 0 dbm. figure 19 . basic loop start application using t7504 type codec r s2 fusible 50 w c vbat1 0.1 m f v bat1 rcvn rts ovh (overhead = 9.2 v for 2.2 vrms ppm) v prog (i limit = 25 ma) v bat lcf c f2 0.015 m f fb2 cf1 vtx rcvp r t3 r rcv r hb1 vfxin gsx v fro dx dr fse fsep mclk asel 1/4 t7504 codec control inputs pcm highway sync and clock C + nstat itr ppmout c rts 0.1 m f ppmin agnd v dd 2.4 v r n2 1 m w 50 w r ring t ring 100 v130 v secondary or ptc fusible or ptc r rtf 400 w ringing source c cc 0.1 m f v cc c dd 0.1 m f v dd ad c tx 0.15 m f r gx 6.34 k w c c1 rsw pt pwr v bat2 /v cc bgnd v bat1 trgdet icm dgnd txi txn vitr protector 180 v330 v secondary protector v ref b3 reset fb1 latch b2 b1 b0 v ref testlev testsig cf2 multiplexed data bus to/from microprocessor per-line to/from microprocessor v bat2 c vbat2 0.1 m f c ppm 0.1 m f c gs 12 nf r tgs 1.74 k w r ppm 17.4 k w r x r t6 r n1 r gp ramped ppm generation 0.7 vrms for 2.2 vrms at t/r 0.33 m f 54.9 k w 47.5 k w 127 k w 59.0 k w 113 k w 49.9 k w 40.2 k w c c2 0.1 m f c n 120 pf 115 k w 59 k w l9310 (gain of 8) r lcth 69.8 k w r vref pr r vprog 23.2 k w 16.9 k w r ovh lcth (10 ma) v ref v ref
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 55 ac applications (continued) first-generation codec ac interface network: complex termination (continued) basic loop start application using t7504 type codec (continued) table 23. l9310 parts list for agere t7504 first-generation codec complex termination, meter pulse application, dual battery operation * see your agere account representative for a recommended secondary protection device. name value tolerance rating function fault protection r pr 50 w 1% fusible or ptc protection resistor. r pt 50 w 1% fusible or ptc protection resistor. protector* 180 v to 320 v ring-side secondary protector. protector* 100 v to 130 v tip-side secondary protector. power supply diode 1n4004 reverse battery current. c vbat1 0.1 m f 20% 100 v filter capacitor. c vbat2 0.1 m f 20% 50 v filter capacitor. c cc 0.1 m f 20% 10 v filter capacitor. c dd 0.1 m f 20% 10 v filter capacitor. c f2 0.01 m f 20% 100 v filter capacitor. dc profile r vprog 23.2 k w 1% 1/16 w with r vref fix dc current limit. r ovh 16.9 k w 1% 1/16 w with r vref fix overhead voltage. r vref 69.8 k w 1% 1/16 w with r vprog fix dc current limit. supervision c rtf 0.1 m f 20% 100 v ring trip filter capacitor. r rtf 1 m w 1% 1/16 w ring trip filter resistor. r rs1 400 w 5% 2 w sets ring trip threshold. r lcth 59 k w 1% 1/16 w with r vref , fix loop supervision threshold. ppm c ppm 0.01 m f 20% 5 v ac-couple ppm input. r ppm 17.4 k w 1% 1/16 w ppm hybrid rejection.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 56 agere systems inc. ac applications (continued) first-generation codec ac interface network: complex termination (continued) basic loop start application using t7504 type codec (continued) table 23. l9310 parts list for agere t7504 first-generation codec complex termination, meter pulse application, dual battery operation (continued) * see your agere account representative for a recommended secondary protection device. name value tolerance rating function ac interface r gx 6.34 k w 1% 1/16 w sets t/r to vitr dc transconductance and gain shaping for complex ter- mination. r tgc r tgs 1.74 k w 1% 1/16 w gain shaping for complex termination. c gs 12 nf 5% 10 v gain shaping for complex termination. c tx 0.1 m f 20% 10 v ac/dc separation. c c1 0.47 m f 20% 10 v dc blocking capacitor. c c2 0.1 m f 20% 10 v dc blocking capacitor. r t3 49.9 k w 1% 1/16 w with r gp and r rcv , sets termination impedance and receive gain. r t6 40.2 k w 1% 1/16 w with r x , sets transmit gain. r x 115 k w 1% 1/16 w with r t6 , sets transmit gain. r hb 113 k w 1% 1/16 w with r x , sets hybrid balance. r rcv 59.0 k w 1% 1/16 w with r gp and r t3 , sets termination impedance and receive gain. r gp 54.9 k w 1% 1/16 w with r rcv and r t3 , sets termination impedance and receive gain. c n 120 pf 20% 10 v high-fr equency compensation. r n1 127 k w 1% 1/16 w high-frequency compensation. r n2 47.5 k w 1% 1/16 w high-frequency compensation, compensate for dc offset at rcvp/rcvn.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 57 ac applications (continued) third-generation codec ac interface network: complex termination the following reference circuit shows the complete slic schematic for interface to the agere t8536 third-genera- tion. all ac parameters are programmed by the t8536. note that this codec differentiates itself in that no external components are required in the ac interface to provide a dc termination impedance or for stability. for illustration purposes, 2.2 vrms ppm injection was assumed in this example, and hybrid meter pulse rejection is used. also, this example illustrates the device using the battery switch with multiple battery operation and programmable over- head, current limit, and loop closure threshold. please see the t8535/6 data sheet for information on coefficient programming. 12-3527f (f) figure 20. l9310 for agere t8536 third-generation codec meter pulse application, dual battery operation, ac and dc parameters, fully programmable r s1 fusible 50 w c vbat1 0.1 m f v bat1 rcvn rts v prog lcth v bat c f2 0.015 m f fb2 cf1 vtx rcvp vfrop vfxin vfron dx0 dr1 fs bclk dgnd v dd pcm highway sync and clock itr ppmout c rts 0.1 m f ppmin agnd v dd 1 m w 50 w r ring 100 v130 v secondary or ptc fusible or ptc r rtf 400 w ringing source c cc 0.1 m f v cc c dd 0.1 m f v dd ad c tx 0.15 m f r gx 6.34 k w c c1 rsw pt v bat2 /v cc bgnd v bat1 trgdet icm dgnd txi txn vitr protector 180 v330 v secondary protector v ref fb1 v ref testlev testsig cf2 per-line to/from microprocessor v bat2 c vbat2 0.1 m f c ppm 0.01 m f r ppm 17.4 k w ramped ppm generation 0.7 vrms for 2.2 vrms at t/r ovh (overhead = 9.2 v for 2.2 vrms ppm) from programmable voltage source pwr t ring reset slic0a slic5a nstat b1 b2 slic3a slic4a slic2a b3 b0 slic1a dr0 dx1 t8536 cv dd 0.1 m f v dd l9310 (gain of 2) lcf pr 0.33 m f reset r lcth r cin 20 m w
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit 58 agere systems inc. ac applications (continued) third-generation codec ac interface network: complex termination (continued) table 24. l9310 parts list for agere t8536 third-generation codec meter pulse application, dual battery operation, ac and dc parameters, fully programmable * see your agere account representative for a recommended secondary protection device. name value tolerance rating function fault protection r pr 50 w 1% fusible or ptc protection resistor. r pt 50 w 1% fusible or ptc protection resistor. protector* 180 v to 320 v ring-side secondary protector. protector* 100 v to 130 v tip-side secondary protector. power supply diode 1n4004 reverse battery current. c vbat1 0.1 m f 20% 100 v filter capacitor. c vbat2 0.1 m f 20% 50 v filter capacitor. c cc 0.1 m f 20% 10 v filter capacitor. c dd 0.1 m f 20% 10 v filter capacitor. c f2 0.015 m f 20% 100 v filter capacitor. supervision c rtf 0.1 m f 20% 100 v ring trip filter capacitor. r rtf 1 m w 1% 1/16 w ring trip filter resistor. r rs1 400 w 5% 2 w sets ring trip threshold. ppm c ppm 0.01 m f 20% 5 v ac couple ppm input. r ppm 17.4 k w 1% 1/16 w ppm hybrid rejection. ac interface r gx 6.34 k w 1% 1/16 w sets t/r to vitr transconductance. r cin 20 m w 5% 1/16 w dc bias. c tx 0.15 m f 20% 10 v ac/dc separation. c c1 0.33 m f 20% 10 v dc blocking capacitor.
data sheet july 2001 full-feature slic, ringing relay, and test access device l9310 line interface and line access circuit agere systems inc. 59 outline diagram 44-pin plcc 5-2506f 4.57 max 1.27 typ 0.53 max 0.10 seating plane 0.51 min typ 1 640 7 17 29 39 18 28 pin #1 identifier zone 16.66 max 17.65 max 16.66 max 17.65 max
a ge r e s y s tem s in c . r e s e r v e s the r i g h t to ma k e c h a nges t o the p r odu c t ( s ) or i nfo r mat i on c o nta i ned he r e i n w i thout n ot i c e. no l i a b ili t y i s a s s u m e d a s a r e s u l t o f t h e i r u s e o r app l i c at i on. cop y r i ght ? 2001 a ge r e s y s te m s in c . a l l r i gh t s re s e r v ed j u l y 2 0 01 ds 0 1 - 1 9 0 a l c (r e p l a c e s ds 0 1 - 1 6 8 a l c) f o r addi t i o nal in f o r m a t io n , c on t a c t y ou r a ge r e sys t e ms a c c o u n t m a n a g e r o r t h e f oll o wing: i n t e r n e t : h tt p : / / w w w . a g e r e . c o m e-ma i l : d o c mas t e r @ m i cr o . lu ce n t . c o m n . a m e r i c a : a g e r e sys t e ms i n c . , 555 un i on b o ule v a r d , roo m 30l - 1 5 p - b a , a l len t ow n , p a 1 8109 - 3 286 1 - 8 00 - 37 2 - 2447 , f a x 6 1 0 - 712 - 4 1 06 ( i n c a n a d a : 1 - 800 - 5 5 3 - 2448 , f a x 6 1 0 - 712 - 4 106) as i a p a c i f i c : a g e r e sys t e ms s i n g apo r e p t e . l t d ., 7 7 s c ie n c e p a r k d r i v e , #03 - 1 8 c i n t e c h i i i , s i ngap o r e 1 182 5 6 t e l . ( 65 ) 77 8 8 8 33 , f a x ( 65 ) 777 74 9 5 c h i n a: a g e r e sys t e ms (s h a n ghai ) co . , l t d . , 3 3 / f j i n m a o t o we r , 8 8 cen t u r y b oule v a r d p u d ong , s h angh a i 2 0012 1 p r c t e l . ( 86 ) 21 50 4 71212 , f a x ( 8 6 ) 2 1 5 0472 2 66 ja p a n : a g e r e sys t e ms j a p a n l t d . , 7 - 1 8 , hi g a s h i - g o t and a 2 - c h o m e, s hi n agaw a - k u , t o k y o 141 , j a pa n t e l . ( 81 ) 3 542 1 1 6 00 , f a x ( 81 ) 3 5 421 17 0 0 e ur o p e : d a t a r equ e s t s : d a t a l i n e : t e l . ( 4 4 ) 7 0 0 0 58 2 36 8 , f a x ( 4 4 ) 1 189 328 148 t e c h n i c al i nqui r i e s : g e r m a n y : ( 4 9 ) 8 9 9 508 6 0 (m uni c h ) , un i t e d k i n g d o m : ( 44 ) 1344 86 5 9 0 0 (asc o t ) , f r a n c e : ( 3 3 ) 1 40 83 68 00 (p a r i s) , s w e d e n : ( 46 ) 8 594 60 7 0 0 ( s t o ck h o l m), f i n l a n d : ( 358 ) 9 350 7 670 ( hel s i n k i ) , i t a l y : ( 39 ) 02 6608 1 31 ( m i lan ) , s p a i n : ( 3 4 ) 1 8 0 7 1 441 (m ad r id) da t a s h e et j u ly 2 001 f ull - fe a tu r e s l i c, rin g in g rela y , a n d t es t acces s device l 931 0 li n e i n te r fa c e a n d l ine a c ces s c i rc u it ordering info r mation device pa r t nu m ber packa g e comc o de luc l 9310ap-d 44-pin plcc, d r y-ba g ged 1 08326 7 29 l ucl931 0 a p-dt 44-pin plcc, dr y -b a gged, t ape and reel 1 08326 7 37 lucl9 3 10gp-d 44-pin plcc, d r y-ba g ged 1 08417 8 66 luc l 9310 g p -dt 44-pin plcc, dr y -b a gged, t ape and reel 1 08417 8 74

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